1a697ccf59
This adds the necessary bits in arch code, and Python scripts to enable coredump support for RISC-V Signed-off-by: Mark Holden <mholden@fb.com>
34 lines
918 B
Python
34 lines
918 B
Python
#!/usr/bin/env python3
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#
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# Copyright (c) 2020 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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from gdbstubs.arch.x86 import GdbStub_x86
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from gdbstubs.arch.x86_64 import GdbStub_x86_64
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from gdbstubs.arch.arm_cortex_m import GdbStub_ARM_CortexM
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from gdbstubs.arch.risc_v import GdbStub_RISC_V
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class TgtCode:
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UNKNOWN = 0
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X86 = 1
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X86_64 = 2
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ARM_CORTEX_M = 3
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RISC_V = 4
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def get_gdbstub(logfile, elffile):
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stub = None
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tgt_code = logfile.log_hdr['tgt_code']
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if tgt_code == TgtCode.X86:
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stub = GdbStub_x86(logfile=logfile, elffile=elffile)
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elif tgt_code == TgtCode.X86_64:
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stub = GdbStub_x86_64(logfile=logfile, elffile=elffile)
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elif tgt_code == TgtCode.ARM_CORTEX_M:
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stub = GdbStub_ARM_CortexM(logfile=logfile, elffile=elffile)
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elif tgt_code == TgtCode.RISC_V:
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stub = GdbStub_RISC_V(logfile=logfile, elffile=elffile)
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return stub
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