3fbd7dfb75
This adds an architecture-specific post processing after memory writes. This introduction is due to GDB's behavior regarding breakpoints in code. GDB may choose to write break instructions instead of using hardware breakpoints to interrupt code execution (e.g. for manual breakpoint or stepping through code). There is no separate GDB packet type for this. So we need to make an assumption that a memory write may be to setup break instructions. Different architectures may have their own unique ways of dealing with instruction cache in this situation. So we defer to the architecture code to handle this. Signed-off-by: Daniel Leung <daniel.leung@intel.com> |
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| .. | ||
| coredump | ||
| coresight | ||
| gdbstub | ||
| symtab | ||
| thread_analyzer | ||
| asan_hacks.c | ||
| CMakeLists.txt | ||
| cpu_load.c | ||
| Kconfig | ||
| mipi_stp_decoder.c | ||
| thread_info.c | ||