94a6b82572
DWC2 otg OUT transfers are being used for SETUP DATA0, OUT Data Stage packets and OUT Status Stage ZLP. On High-Speed it is possible for IN Data Stage, OUT Status Stage ZLP and subsequent SETUP DATA0 to happen in very quick succession, making all the three events appear at the same time to the handler thread. The handler thread is picking up next endpoint to handle based on the least significant bit set. When OUT endpoints were on bits 0-15 and IN endpoints were on bits 16-31, the least significant bit policy favored OUT endpoints over IN endpoints. This caused problems in Completer mode (but suprisingly not in Buffer DMA mode) that lead to incorrect control transfer handling. The choice between least significant bit first or most significant bit first is arbitrary. Switching from least to most significant bit first would have resolved the issue. It would also favor higher numbered endpoints over lower numbered endpoints. Swap the order of endpoints in bitmaps to have IN on bits 0-15 and OUT on bits 16-31 to keep handling lower numbered endpoints first and resolve the control transfer handling in Completer mode. Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no> |
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| .. | ||
| bc12 | ||
| common | ||
| device | ||
| udc | ||
| uhc | ||
| uvb | ||
| CMakeLists.txt | ||
| Kconfig | ||