94cc9a9bdb
Change fixes a build warning related to attribute ignored in declaration of struct. The __packed attribute is removed. Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
136 lines
3.5 KiB
C
136 lines
3.5 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Per-arch thread definition
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*
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* This file contains definitions for
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*
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* struct _thread_arch
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* struct _callee_saved
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*
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* necessary to instantiate instances of struct k_thread.
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_THREAD_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_THREAD_H_
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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struct _callee_saved {
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uint32_t v1; /* r4 */
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uint32_t v2; /* r5 */
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uint32_t v3; /* r6 */
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uint32_t v4; /* r7 */
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uint32_t v5; /* r8 */
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uint32_t v6; /* r9 */
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uint32_t v7; /* r10 */
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uint32_t v8; /* r11 */
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uint32_t psp; /* r13 */
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};
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typedef struct _callee_saved _callee_saved_t;
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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struct _preempt_float {
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float s16;
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float s17;
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float s18;
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float s19;
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float s20;
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float s21;
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float s22;
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float s23;
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float s24;
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float s25;
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float s26;
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float s27;
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float s28;
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float s29;
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float s30;
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float s31;
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};
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#endif
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struct _thread_arch {
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/* interrupt locking key */
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uint32_t basepri;
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/* r0 in stack frame cannot be written to reliably */
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uint32_t swap_return_value;
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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/*
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* No cooperative floating point register set structure exists for
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* the Cortex-M as it automatically saves the necessary registers
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* in its exception stack frame.
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*/
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struct _preempt_float preempt_float;
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#endif
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#if defined(CONFIG_ARM_STORE_EXC_RETURN) || defined(CONFIG_USERSPACE)
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/*
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* Status variable holding several thread status flags
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* as follows:
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*
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* byte 0
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* +-bits 4-7-----bit-3----------bit-2--------bit-1---+----bit-0------+
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* : | | | | |
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* : reserved |<Guard FLOAT>| reserved | reserved | <priv mode> |
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* : bits | | | | CONTROL.nPRIV |
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* +------------------------------------------------------------------+
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*
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* byte 1
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* +----------------------------bits 8-15-----------------------------+
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* : Least significant byte of EXC_RETURN |
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* : bit 15| bit 14| bit 13 | bit 12| bit 11 | bit 10 | bit 9 | bit 8 |
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* : Res | S | DCRS | FType | Mode | SPSel | Res | ES |
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* +------------------------------------------------------------------+
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*
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* Bit 0: thread's current privileged mode (Supervisor or User mode)
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* Mirrors CONTROL.nPRIV flag.
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* Bit 2: Deprecated in favor of FType. Note: FType = !CONTROL.FPCA.
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* indicating whether the thread has an active FP context.
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* Mirrors CONTROL.FPCA flag.
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* Bit 3: indicating whether the thread is applying the long (FLOAT)
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* or the default MPU stack guard size.
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*
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* Bits 8-15: Least significant octet of the EXC_RETURN value when a
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* thread is switched-out. The value is copied from LR when
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* entering the PendSV handler. When the thread is
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* switched in again, the value is restored to LR before
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* exiting the PendSV handler.
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*/
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union {
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uint32_t mode;
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#if defined(CONFIG_ARM_STORE_EXC_RETURN)
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struct {
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uint8_t mode_bits;
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uint8_t mode_exc_return;
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uint16_t mode_reserved2;
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};
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#endif
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};
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#if defined(CONFIG_USERSPACE)
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uint32_t priv_stack_start;
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#endif
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#endif
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};
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#if defined(CONFIG_FPU_SHARING) && defined(CONFIG_MPU_STACK_GUARD)
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#define Z_ARM_MODE_MPU_GUARD_FLOAT_Msk (1 << 3)
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#endif
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typedef struct _thread_arch _thread_arch_t;
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_THREAD_H_ */
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