706de953ab
If we try and build the MiV uart driver with interrupt support enabled we get some errors related to code that hasn't been updated. Fix the compile errors and add SERIAL_SUPPORT_INTERRUPT to the Kconfig to hopefully catch these issues in the future Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
430 lines
10 KiB
C
430 lines
10 KiB
C
/*
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* Copyright (c) 2018 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microsemi_coreuart
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <drivers/uart.h>
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/* UART REGISTERS DEFINITIONS */
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/* TX register */
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#define TXDATA_REG_OFFSET 0x0
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#define TXDATA_OFFSET 0x0
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#define TXDATA_MASK 0xFF
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#define TXDATA_SHIFT 0
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/* RX register */
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#define RXDATA_REG_OFFSET 0x4
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#define RXDATA_OFFSET 0x4
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#define RXDATA_MASK 0xFF
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#define RXDATA_SHIFT 0
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/* Control1 register */
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#define CTRL1_REG_OFFSET 0x8
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/* Baud value lower 8 bits */
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#define CTRL1_BAUDVALUE_OFFSET 0x8
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#define CTRL1_BAUDVALUE_MASK 0xFF
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#define CTRL1_BAUDVALUE_SHIFT 0
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/* Control2 register */
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#define CTRL2_REG_OFFSET 0xC
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/* Bit length */
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#define CTRL2_BIT_LENGTH_OFFSET 0xC
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#define CTRL2_BIT_LENGTH_MASK 0x01
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#define CTRL2_BIT_LENGTH_SHIFT 0
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/* Parity enable */
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#define CTRL2_PARITY_EN_OFFSET 0xC
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#define CTRL2_PARITY_EN_MASK 0x02
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#define CTRL2_PARITY_EN_SHIFT 1
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/* Odd/even parity configuration */
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#define CTRL2_ODD_EVEN_OFFSET 0xC
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#define CTRL2_ODD_EVEN_MASK 0x04
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#define CTRL2_ODD_EVEN_SHIFT 2
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/* Baud value higher 5 bits */
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#define CTRL2_BAUDVALUE_OFFSET 0xC
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#define CTRL2_BAUDVALUE_MASK 0xF8
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#define CTRL2_BAUDVALUE_SHIFT 3
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/* Status register */
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#define StatusReg_REG_OFFSET 0x10
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#define STATUS_REG_OFFSET 0x10
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/* TX ready */
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#define STATUS_TXRDY_OFFSET 0x10
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#define STATUS_TXRDY_MASK 0x01
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#define STATUS_TXRDY_SHIFT 0
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/* Receive full - raised even when 1 char arrived */
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#define STATUS_RXFULL_OFFSET 0x10
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#define STATUS_RXFULL_MASK 0x02
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#define STATUS_RXFULL_SHIFT 1
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/* Parity error */
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#define STATUS_PARITYERR_OFFSET 0x10
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#define STATUS_PARITYERR_MASK 0x04
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#define STATUS_PARITYERR_SHIFT 2
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/* Overflow */
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#define STATUS_OVERFLOW_OFFSET 0x10
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#define STATUS_OVERFLOW_MASK 0x08
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#define STATUS_OVERFLOW_SHIFT 3
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/* Frame error */
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#define STATUS_FRAMERR_OFFSET 0x10
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#define STATUS_FRAMERR_MASK 0x10
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#define STATUS_FRAMERR_SHIFT 4
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/* Data bits length defines */
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#define DATA_7_BITS 0x00
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#define DATA_8_BITS 0x01
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/* Parity defines */
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#define NO_PARITY 0x00
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#define EVEN_PARITY 0x02
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#define ODD_PARITY 0x06
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/* Error Status definitions */
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#define UART_PARITY_ERROR 0x01
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#define UART_OVERFLOW_ERROR 0x02
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#define UART_FRAMING_ERROR 0x04
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#define BAUDVALUE_LSB ((uint16_t)(0x00FF))
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#define BAUDVALUE_MSB ((uint16_t)(0xFF00))
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#define BAUDVALUE_SHIFT ((uint8_t)(5))
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static struct k_thread rx_thread;
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static K_KERNEL_STACK_DEFINE(rx_stack, 512);
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#endif
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struct uart_miv_regs_t {
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uint8_t tx;
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uint8_t reserved0[3];
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uint8_t rx;
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uint8_t reserved1[3];
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uint8_t ctrlreg1;
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uint8_t reserved2[3];
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uint8_t ctrlreg2;
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uint8_t reserved3[3];
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uint8_t status;
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};
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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typedef void (*irq_cfg_func_t)(const struct device *dev);
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#endif
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struct uart_miv_device_config {
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uint32_t uart_addr;
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uint32_t sys_clk_freq;
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uint32_t line_config;
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uint32_t baud_rate;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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irq_cfg_func_t cfg_func;
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#endif
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};
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struct uart_miv_data {
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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const struct device *dev;
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uart_irq_callback_user_data_t callback;
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void *cb_data;
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#endif
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};
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#define DEV_CFG(dev) \
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((const struct uart_miv_device_config * const) \
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(dev)->config)
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#define DEV_UART(dev) \
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((struct uart_miv_regs_t *)(DEV_CFG(dev))->uart_addr)
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#define DEV_DATA(dev) \
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((struct uart_miv_data * const)(dev)->data)
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static void uart_miv_poll_out(const struct device *dev,
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unsigned char c)
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{
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volatile struct uart_miv_regs_t *uart = DEV_UART(dev);
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while (!(uart->status & STATUS_TXRDY_MASK)) {
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}
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uart->tx = c;
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}
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static int uart_miv_poll_in(const struct device *dev, unsigned char *c)
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{
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volatile struct uart_miv_regs_t *uart = DEV_UART(dev);
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if (uart->status & STATUS_RXFULL_MASK) {
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*c = (unsigned char)(uart->rx & RXDATA_MASK);
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return 0;
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}
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return -1;
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}
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static int uart_miv_err_check(const struct device *dev)
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{
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volatile struct uart_miv_regs_t *uart = DEV_UART(dev);
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uint32_t flags = uart->status;
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int err = 0;
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if (flags & STATUS_PARITYERR_MASK) {
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err |= UART_PARITY_ERROR;
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}
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if (flags & STATUS_OVERFLOW_MASK) {
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err |= UART_OVERFLOW_ERROR;
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}
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if (flags & STATUS_FRAMERR_MASK) {
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err |= UART_FRAMING_ERROR;
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}
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return err;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_miv_fifo_fill(const struct device *dev,
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const uint8_t *tx_data,
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int size)
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{
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volatile struct uart_miv_regs_t *uart = DEV_UART(dev);
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int i;
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for (i = 0; i < size && (uart->status & STATUS_TXRDY_MASK); i++) {
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uart->tx = tx_data[i];
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}
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return i;
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}
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static int uart_miv_fifo_read(const struct device *dev,
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uint8_t *rx_data,
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const int size)
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{
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volatile struct uart_miv_regs_t *uart = DEV_UART(dev);
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int i;
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for (i = 0; i < size; i++) {
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if (uart->status & STATUS_RXFULL_MASK) {
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rx_data[i] = (unsigned char)(uart->rx & RXDATA_MASK);
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} else {
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break;
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}
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}
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return i;
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}
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static void uart_miv_irq_tx_enable(const struct device *dev)
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{
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ARG_UNUSED(dev);
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}
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static void uart_miv_irq_tx_disable(const struct device *dev)
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{
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ARG_UNUSED(dev);
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}
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static int uart_miv_irq_tx_ready(const struct device *dev)
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{
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volatile struct uart_miv_regs_t *uart = DEV_UART(dev);
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return !(uart->status & STATUS_TXRDY_MASK);
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}
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static int uart_miv_irq_tx_complete(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 1;
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}
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static void uart_miv_irq_rx_enable(const struct device *dev)
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{
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ARG_UNUSED(dev);
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}
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static void uart_miv_irq_rx_disable(const struct device *dev)
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{
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ARG_UNUSED(dev);
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}
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static int uart_miv_irq_rx_ready(const struct device *dev)
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{
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volatile struct uart_miv_regs_t *uart = DEV_UART(dev);
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return !!(uart->status & STATUS_RXFULL_MASK);
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}
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static void uart_miv_irq_err_enable(const struct device *dev)
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{
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ARG_UNUSED(dev);
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}
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static void uart_miv_irq_err_disable(const struct device *dev)
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{
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ARG_UNUSED(dev);
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}
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static int uart_miv_irq_is_pending(const struct device *dev)
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{
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volatile struct uart_miv_regs_t *uart = DEV_UART(dev);
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return !!(uart->status & STATUS_RXFULL_MASK);
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}
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static int uart_miv_irq_update(const struct device *dev)
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{
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return 1;
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}
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static void uart_miv_irq_handler(const struct device *dev)
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{
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struct uart_miv_data *data = DEV_DATA(dev);
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if (data->callback) {
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data->callback(dev, data->cb_data);
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}
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}
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/*
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* This thread is a workaround for IRQs that are not connected in Mi-V.
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* Since we cannot rely on IRQs, the rx_thread is working instead and
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* polling for data. The thread calls the registered callback when data
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* arrives.
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*/
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void uart_miv_rx_thread(void *arg1, void *arg2, void *arg3)
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{
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struct uart_miv_data *data = (struct uart_miv_data *)arg1;
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const struct device *dev = data->dev;
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volatile struct uart_miv_regs_t *uart = DEV_UART(dev);
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const struct uart_miv_device_config *const cfg = DEV_CFG(dev);
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/* Make it go to sleep for a period no longer than
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* time to receive next character.
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*/
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uint32_t delay = 1000000 / cfg->baud_rate;
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ARG_UNUSED(arg2);
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ARG_UNUSED(arg3);
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while (1) {
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if (uart->status & STATUS_RXFULL_MASK) {
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uart_miv_irq_handler(dev);
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}
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k_sleep(K_USEC(delay));
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}
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}
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static void uart_miv_irq_callback_set(const struct device *dev,
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uart_irq_callback_user_data_t cb,
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void *cb_data)
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{
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struct uart_miv_data *data = DEV_DATA(dev);
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data->callback = cb;
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data->cb_data = cb_data;
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static int uart_miv_init(const struct device *dev)
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{
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const struct uart_miv_device_config *const cfg = DEV_CFG(dev);
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volatile struct uart_miv_regs_t *uart = DEV_UART(dev);
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/* Calculate divider value to set baudrate */
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uint16_t baud_value = (cfg->sys_clk_freq / (cfg->baud_rate * 16U)) - 1;
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/* Set baud rate */
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uart->ctrlreg1 = (uint8_t)(baud_value & BAUDVALUE_LSB);
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uart->ctrlreg2 = (uint8_t)(cfg->line_config) |
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(uint8_t)((baud_value & BAUDVALUE_MSB) >> BAUDVALUE_SHIFT);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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/* Setup thread polling for data */
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cfg->cfg_func(dev);
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#endif
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return 0;
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}
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static const struct uart_driver_api uart_miv_driver_api = {
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.poll_in = uart_miv_poll_in,
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.poll_out = uart_miv_poll_out,
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.err_check = uart_miv_err_check,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_miv_fifo_fill,
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.fifo_read = uart_miv_fifo_read,
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.irq_tx_enable = uart_miv_irq_tx_enable,
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.irq_tx_disable = uart_miv_irq_tx_disable,
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.irq_tx_ready = uart_miv_irq_tx_ready,
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.irq_tx_complete = uart_miv_irq_tx_complete,
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.irq_rx_enable = uart_miv_irq_rx_enable,
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.irq_rx_disable = uart_miv_irq_rx_disable,
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.irq_rx_ready = uart_miv_irq_rx_ready,
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.irq_err_enable = uart_miv_irq_err_enable,
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.irq_err_disable = uart_miv_irq_err_disable,
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.irq_is_pending = uart_miv_irq_is_pending,
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.irq_update = uart_miv_irq_update,
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.irq_callback_set = uart_miv_irq_callback_set,
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#endif
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};
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/* This driver is single-instance. */
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
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"unsupported uart_miv instance");
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#if DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay)
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static struct uart_miv_data uart_miv_data_0;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void uart_miv_irq_cfg_func_0(const struct device *dev);
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#endif
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static const struct uart_miv_device_config uart_miv_dev_cfg_0 = {
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.uart_addr = DT_INST_REG_ADDR(0),
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.sys_clk_freq = DT_INST_PROP(0, clock_frequency),
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.line_config = MIV_UART_0_LINECFG,
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.baud_rate = DT_INST_PROP(0, current_speed),
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.cfg_func = uart_miv_irq_cfg_func_0,
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#endif
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};
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DEVICE_DT_INST_DEFINE(0, uart_miv_init, NULL,
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&uart_miv_data_0, &uart_miv_dev_cfg_0,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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(void *)&uart_miv_driver_api);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void uart_miv_irq_cfg_func_0(const struct device *dev)
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{
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struct uart_miv_data *data = DEV_DATA(dev);
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data->dev = dev;
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/* Create a thread which will poll for data - replacement for IRQ */
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k_thread_create(&rx_thread, rx_stack, 500,
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uart_miv_rx_thread, data, NULL, NULL, K_PRIO_COOP(2),
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0, K_NO_WAIT);
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}
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#endif
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#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) */
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