42aeaccb3e
NPCX clock has some limitations about the frequency range & synchronization between core clock & other clocks. Add build assert to check whether NPCX clock setting correct. This also fixed soc_clock.h to consist with datasheet. Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
71 lines
2.2 KiB
Plaintext
71 lines
2.2 KiB
Plaintext
# NPCX Clock controller driver configuration options
|
|
|
|
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
config CLOCK_CONTROL_NPCX
|
|
bool "NPCX clock controller driver"
|
|
depends on SOC_FAMILY_NPCX
|
|
help
|
|
Enable support for NPCX clock controller driver.
|
|
|
|
config CLOCK_NPCX_OSC_CYCLES_PER_SEC
|
|
int "CDCG PLL frequency"
|
|
default 48000000
|
|
range 10000000 100000000
|
|
depends on SOC_FAMILY_NPCX
|
|
help
|
|
Core Domain Clock (OSC_CLK) Generator PLL frequency,
|
|
allowed values: From 10Mhz to 100Mhz.
|
|
|
|
config CLOCK_NPCX_APB1_PRESCALER
|
|
int "APB1 prescaler"
|
|
default 4
|
|
range 1 10
|
|
depends on SOC_FAMILY_NPCX
|
|
help
|
|
This sets the APB1 prescaler which changes the frequency of APB1_CLK.
|
|
APB1_CLK frequency = OSC_CLK / APB1_PRE. The APB1 prescaler allowed
|
|
value is from 1 to 10.
|
|
|
|
The generated frequency of APB1_CLK should comply with the following
|
|
requirements:
|
|
- The frequency of APB1_CLK must be set to:
|
|
4MHz <= APB1_CLK <= 50MHz.
|
|
- The frequency of APB1_CLK must be an integer division (including 1)
|
|
of the frequency of the Core clock.
|
|
|
|
config CLOCK_NPCX_APB2_PRESCALER
|
|
int "APB2 prescaler"
|
|
default 8
|
|
range 1 10
|
|
depends on SOC_FAMILY_NPCX
|
|
help
|
|
This sets the APB2 prescaler which changes the frequency of APB2_CLK.
|
|
APB2_CLK frequency = OSC_CLK / APB2_PRE. The APB2 prescaler allowed
|
|
value is from 1 to 10.
|
|
|
|
The generated frequency of APB2_CLK should comply with the following
|
|
requirements:
|
|
- The frequency of APB2_CLK must be set to:
|
|
8MHz <= APB2_CLK <= 50MHz.
|
|
- The frequency of APB2_CLK must be an integer division (including 1)
|
|
of the frequency of the Core clock.
|
|
|
|
config CLOCK_NPCX_APB3_PRESCALER
|
|
int "APB3 prescaler"
|
|
default 2
|
|
range 1 10
|
|
depends on SOC_FAMILY_NPCX
|
|
help
|
|
This sets the APB3 prescaler which changes the frequency of APB3_CLK.
|
|
APB3_CLK frequency = OSC_CLK / APB3_PRE. The APB3 prescaler allowed
|
|
value is from 1 to 10.
|
|
|
|
The generated frequency of APB3_CLK should comply with the following
|
|
requirements:
|
|
- The frequency of APB3_CLK must be set to:
|
|
12.5MHz <= APB3_CLK <= 50MHz.
|
|
- The frequency of APB3_CLK must be an integer division (including 1)
|
|
of the frequency of the Core clock.
|