f8a909dad1
Adds the necessary bits to initialize TLS in the stack area and sets up CPU registers during context switch. Note that this does not enable TLS for all Xtensa SoC. This is because Xtensa SoCs are highly configurable so that each SoC can be considered a whole architecture. So TLS needs to be enabled on the SoC level, instead of at the arch level. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
25 lines
853 B
C
25 lines
853 B
C
/*
|
|
* Copyright (c) 2017, Intel Corporation
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
#ifndef ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_H_
|
|
#define ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_H_
|
|
|
|
#include <kernel_structs.h>
|
|
#include "xtensa-asm2-context.h"
|
|
|
|
/**
|
|
* Initializes a stack area such that it can be "restored" later and
|
|
* begin running with the specified function and three arguments. The
|
|
* entry function takes three arguments to match the signature of
|
|
* Zephyr's k_thread_entry_t. Thread will start with EXCM clear and
|
|
* INTLEVEL set to zero (i.e. it's a user thread, we don't start with
|
|
* anything masked, so don't assume that!).
|
|
*/
|
|
void *xtensa_init_stack(struct k_thread *thread, int *stack_top,
|
|
void (*entry)(void *, void *, void *),
|
|
void *arg1, void *arg2, void *arg3);
|
|
|
|
#endif /* ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_H_ */
|