f8a909dad1
Adds the necessary bits to initialize TLS in the stack area and sets up CPU registers during context switch. Note that this does not enable TLS for all Xtensa SoC. This is because Xtensa SoCs are highly configurable so that each SoC can be considered a whole architecture. So TLS needs to be enabled on the SoC level, instead of at the arch level. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <kernel_structs.h>
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#include <kernel_internal.h>
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#include <kernel_tls.h>
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#include <app_memory/app_memdomain.h>
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#include <sys/util.h>
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#if XCHAL_HAVE_THREADPTR == 0
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#error SoC does not support THREADPTR for thread local storage.
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#endif
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size_t arch_tls_stack_setup(struct k_thread *new_thread, char *stack_ptr)
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{
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/*
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* TLS area has some data fields following by
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* thread data and bss. These fields are supposed to be
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* used by toolchain and OS TLS code to aid in locating
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* the TLS data/bss. Zephyr currently has no use for
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* this so we can simply skip these. However, since GCC
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* is generating code assuming these fields are there,
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* we simply skip them when setting the TLS pointer.
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*/
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/*
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* Since we are populating things backwards,
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* setup the TLS data/bss area first.
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*/
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stack_ptr -= z_tls_data_size();
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z_tls_copy(stack_ptr);
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/* Skip two pointers due to toolchain */
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stack_ptr -= sizeof(uintptr_t) * 2;
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/*
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* Set thread TLS pointer which is used in
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* context switch to point to TLS area.
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*/
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new_thread->tls = POINTER_TO_UINT(stack_ptr);
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return (z_tls_data_size() + (sizeof(uintptr_t) * 2));
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}
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