d6cbdace78
There is a possibility that the TSC frequency calculation is divided by zero. So this fixes the issue by repeatedly trying to get the delta clock cycles and delta TSC cycles until they both are not zero. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
92 lines
1.7 KiB
C
92 lines
1.7 KiB
C
/*
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* Copyright (c) 2020 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/x86/arch.h>
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#include <kernel.h>
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#include <sys_clock.h>
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#include <timing/timing.h>
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#include <app_memory/app_memdomain.h>
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K_APP_BMEM(z_libc_partition) static uint64_t tsc_freq;
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void arch_timing_x86_init(void)
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{
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uint32_t cyc_start, cyc_end;
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uint64_t tsc_start, tsc_end;
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uint64_t cyc_freq = sys_clock_hw_cycles_per_sec();
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uint64_t dcyc, dtsc;
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do {
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cyc_start = k_cycle_get_32();
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tsc_start = z_tsc_read();
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k_busy_wait(10 * USEC_PER_MSEC);
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cyc_end = k_cycle_get_32();
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tsc_end = z_tsc_read();
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/*
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* cycles are in 32-bit, and delta must be
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* calculated in 32-bit percision. Or it would
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* wrapping around in 64-bit.
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*/
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dcyc = (uint32_t)cyc_end - (uint32_t)cyc_start;
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dtsc = tsc_end - tsc_start;
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} while ((dcyc == 0) || (dtsc == 0));
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tsc_freq = (cyc_freq * dtsc) / dcyc;
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}
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uint64_t arch_timing_x86_freq_get(void)
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{
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return tsc_freq;
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}
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void arch_timing_init(void)
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{
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arch_timing_x86_init();
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}
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void arch_timing_start(void)
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{
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}
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void arch_timing_stop(void)
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{
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}
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timing_t arch_timing_counter_get(void)
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{
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return z_tsc_read();
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}
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uint64_t arch_timing_cycles_get(volatile timing_t *const start,
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volatile timing_t *const end)
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{
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return (*end - *start);
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}
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uint64_t arch_timing_freq_get(void)
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{
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return arch_timing_x86_freq_get();
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}
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uint64_t arch_timing_cycles_to_ns(uint64_t cycles)
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{
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return ((cycles) * NSEC_PER_SEC / tsc_freq);
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}
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uint64_t arch_timing_cycles_to_ns_avg(uint64_t cycles, uint32_t count)
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{
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return arch_timing_cycles_to_ns(cycles) / count;
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}
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uint32_t arch_timing_freq_get_mhz(void)
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{
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return (uint32_t)(arch_timing_freq_get() / 1000000U);
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}
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