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zephyr/arch/riscv/core
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Flavio Ceolin b7d04487e1 arch: riscv: Fix 10.4 violations 
Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential
type category.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2021-04-10 09:59:37 -04:00
..
offsets arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
pmp arch: riscv: Fix 10.4 violations 2021-04-10 09:59:37 -04:00
CMakeLists.txt arch: riscv: add common stub reboot function 2021-03-04 11:09:51 -06:00
cpu_idle.c
fatal.c riscv: MTVAL CSR not supported on OpenISA RV32M1 2021-04-08 14:22:54 +02:00
irq_manage.c kernel: Cleanup logger setup in kernel files 2020-11-27 09:56:34 -05:00
irq_offload.c
isr.S tracing: roll thread switch in/out into thread stats functions 2020-11-11 23:55:49 -05:00
prep_c.c arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
reboot.c arch: riscv: add common stub reboot function 2021-03-04 11:09:51 -06:00
reset.S arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
swap.S
thread.c kernel: arch: introduce k_float_enable() 2021-03-25 14:13:23 +01:00
tls.c
userspace.S arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00