f1f63dda17
This adds FPU sharing support with a lazy context switching algorithm. Every thread is allowed to use FPU/SIMD registers. In fact, the compiler may insert FPU reg accesses in anycontext to optimize even non-FP code unless the -mgeneral-regs-only compiler flag is used, but Zephyr currently doesn't support such a build. It is therefore possible to do FP access in IRS as well with this patch although IRQs are then disabled to prevent nested IRQs in such cases. Because the thread object grows in size, some tests have to be adjusted. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com<
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Private kernel definitions (ARM64)
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*
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* This file contains private kernel function definitions and various
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* other definitions for the ARM Cortex-A processor architecture family.
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*
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* This file is also included by assembly language files which must #define
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* _ASMLANGUAGE before including this header file. Note that kernel
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* assembly source files obtains structure offset values via "absolute symbols"
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* in the offsets.o module.
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*/
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#ifndef ZEPHYR_ARCH_ARM64_INCLUDE_KERNEL_ARCH_FUNC_H_
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#define ZEPHYR_ARCH_ARM64_INCLUDE_KERNEL_ARCH_FUNC_H_
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#include <kernel_arch_data.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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static ALWAYS_INLINE void arch_kernel_init(void)
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{
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}
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static inline void arch_switch(void *switch_to, void **switched_from)
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{
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z_arm64_call_svc(switch_to, switched_from);
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return;
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}
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extern void z_arm64_fatal_error(z_arch_esf_t *esf, unsigned int reason);
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extern void z_arm64_userspace_enter(z_arch_esf_t *esf, uintptr_t sp_el0);
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extern void z_arm64_set_ttbr0(uintptr_t ttbr0);
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extern void z_arm64_ptable_ipi(void);
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#ifdef CONFIG_FPU_SHARING
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void z_arm64_flush_local_fpu(void);
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void z_arm64_flush_fpu_ipi(unsigned int cpu);
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#endif
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_ARCH_ARM64_INCLUDE_KERNEL_ARCH_FUNC_H_ */
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