f1f63dda17
This adds FPU sharing support with a lazy context switching algorithm. Every thread is allowed to use FPU/SIMD registers. In fact, the compiler may insert FPU reg accesses in anycontext to optimize even non-FP code unless the -mgeneral-regs-only compiler flag is used, but Zephyr currently doesn't support such a build. It is therefore possible to do FP access in IRS as well with this patch although IRQs are then disabled to prevent nested IRQs in such cases. Because the thread object grows in size, some tests have to be adjusted. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
66 lines
1.5 KiB
ArmAsm
66 lines
1.5 KiB
ArmAsm
/*
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* Copyright (c) 2021 BayLibre SAS
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* Written by: Nicolas Pitre
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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_ASM_FILE_PROLOGUE
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GTEXT(z_arm64_fpu_save)
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SECTION_FUNC(TEXT, z_arm64_fpu_save)
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stp q0, q1, [x0, #(16 * 0)]
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stp q2, q3, [x0, #(16 * 2)]
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stp q4, q5, [x0, #(16 * 4)]
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stp q6, q7, [x0, #(16 * 6)]
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stp q8, q9, [x0, #(16 * 8)]
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stp q10, q11, [x0, #(16 * 10)]
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stp q12, q13, [x0, #(16 * 12)]
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stp q14, q15, [x0, #(16 * 14)]
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stp q16, q17, [x0, #(16 * 16)]
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stp q18, q19, [x0, #(16 * 18)]
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stp q20, q21, [x0, #(16 * 20)]
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stp q22, q23, [x0, #(16 * 22)]
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stp q24, q25, [x0, #(16 * 24)]
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stp q26, q27, [x0, #(16 * 26)]
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stp q28, q29, [x0, #(16 * 28)]
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stp q30, q31, [x0, #(16 * 30)]
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mrs x1, fpsr
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mrs x2, fpcr
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str w1, [x0, #(16 * 32 + 0)]
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str w2, [x0, #(16 * 32 + 4)]
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ret
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GTEXT(z_arm64_fpu_restore)
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SECTION_FUNC(TEXT, z_arm64_fpu_restore)
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ldp q0, q1, [x0, #(16 * 0)]
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ldp q2, q3, [x0, #(16 * 2)]
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ldp q4, q5, [x0, #(16 * 4)]
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ldp q6, q7, [x0, #(16 * 6)]
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ldp q8, q9, [x0, #(16 * 8)]
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ldp q10, q11, [x0, #(16 * 10)]
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ldp q12, q13, [x0, #(16 * 12)]
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ldp q14, q15, [x0, #(16 * 14)]
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ldp q16, q17, [x0, #(16 * 16)]
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ldp q18, q19, [x0, #(16 * 18)]
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ldp q20, q21, [x0, #(16 * 20)]
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ldp q22, q23, [x0, #(16 * 22)]
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ldp q24, q25, [x0, #(16 * 24)]
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ldp q26, q27, [x0, #(16 * 26)]
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ldp q28, q29, [x0, #(16 * 28)]
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ldp q30, q31, [x0, #(16 * 30)]
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ldr w1, [x0, #(16 * 32 + 0)]
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ldr w2, [x0, #(16 * 32 + 4)]
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msr fpsr, x1
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msr fpcr, x2
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ret
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