a2cfb8431d
This adds code to swap_helper.S which does special handling of LR when the interrupt came from secure. The LR value is stored to memory, and put back into LR when swapping back to the relevant thread. Also, add special handling of FP state when switching from secure to non-secure, since we don't know whether the original non-secure thread (which called a secure service) was using FP registers, so we always store them, just in case. Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
629 lines
19 KiB
C
629 lines
19 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief New thread creation for ARM Cortex-M and Cortex-R
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*
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* Core thread related primitives for the ARM Cortex-M and Cortex-R
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* processor architecture.
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*/
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#include <kernel.h>
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#include <ksched.h>
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#include <wait_q.h>
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#if (MPU_GUARD_ALIGN_AND_SIZE_FLOAT > MPU_GUARD_ALIGN_AND_SIZE)
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#define FP_GUARD_EXTRA_SIZE (MPU_GUARD_ALIGN_AND_SIZE_FLOAT - \
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MPU_GUARD_ALIGN_AND_SIZE)
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#else
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#define FP_GUARD_EXTRA_SIZE 0
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#endif
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#ifndef EXC_RETURN_FTYPE
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/* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
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#define EXC_RETURN_FTYPE (0x00000010UL)
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#endif
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/* Default last octet of EXC_RETURN, for threads that have not run yet.
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* The full EXC_RETURN value will be e.g. 0xFFFFFFBC.
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*/
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#if defined(CONFIG_ARM_NONSECURE_FIRMWARE)
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#define DEFAULT_EXC_RETURN 0xBC;
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#else
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#define DEFAULT_EXC_RETURN 0xFD;
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#endif
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#if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_CPU_CORTEX_M)
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extern K_THREAD_STACK_DEFINE(z_main_stack, CONFIG_MAIN_STACK_SIZE);
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#endif
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/* An initial context, to be "restored" by z_arm_pendsv(), is put at the other
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* end of the stack, and thus reusable by the stack when not needed anymore.
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*
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* The initial context is an exception stack frame (ESF) since exiting the
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* PendSV exception will want to pop an ESF. Interestingly, even if the lsb of
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* an instruction address to jump to must always be set since the CPU always
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* runs in thumb mode, the ESF expects the real address of the instruction,
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* with the lsb *not* set (instructions are always aligned on 16 bit
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* halfwords). Since the compiler automatically sets the lsb of function
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* addresses, we have to unset it manually before storing it in the 'pc' field
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* of the ESF.
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*/
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void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
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char *stack_ptr, k_thread_entry_t entry,
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void *p1, void *p2, void *p3)
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{
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struct __basic_sf *iframe;
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#ifdef CONFIG_MPU_STACK_GUARD
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#if defined(CONFIG_USERSPACE)
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if (z_stack_is_user_capable(stack)) {
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/* Guard area is carved-out of the buffer instead of reserved
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* for stacks that can host user threads
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*/
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thread->stack_info.start += MPU_GUARD_ALIGN_AND_SIZE;
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thread->stack_info.size -= MPU_GUARD_ALIGN_AND_SIZE;
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}
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#endif /* CONFIG_USERSPACE */
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#if FP_GUARD_EXTRA_SIZE > 0
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if ((thread->base.user_options & K_FP_REGS) != 0) {
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/* Larger guard needed due to lazy stacking of FP regs may
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* overshoot the guard area without writing anything. We
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* carve it out of the stack buffer as-needed instead of
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* unconditionally reserving it.
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*/
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thread->stack_info.start += FP_GUARD_EXTRA_SIZE;
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thread->stack_info.size -= FP_GUARD_EXTRA_SIZE;
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}
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#endif /* FP_GUARD_EXTRA_SIZE */
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#endif /* CONFIG_MPU_STACK_GUARD */
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iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
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#if defined(CONFIG_USERSPACE)
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if ((thread->base.user_options & K_USER) != 0) {
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iframe->pc = (uint32_t)arch_user_mode_enter;
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} else {
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iframe->pc = (uint32_t)z_thread_entry;
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}
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#else
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iframe->pc = (uint32_t)z_thread_entry;
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#endif
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#if defined(CONFIG_CPU_CORTEX_M)
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/* force ARM mode by clearing LSB of address */
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iframe->pc &= 0xfffffffe;
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#endif
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iframe->a1 = (uint32_t)entry;
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iframe->a2 = (uint32_t)p1;
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iframe->a3 = (uint32_t)p2;
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iframe->a4 = (uint32_t)p3;
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#if defined(CONFIG_CPU_CORTEX_M)
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iframe->xpsr =
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0x01000000UL; /* clear all, thumb bit is 1, even if RO */
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#else
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iframe->xpsr = A_BIT | MODE_SYS;
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#if defined(CONFIG_COMPILER_ISA_THUMB2)
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iframe->xpsr |= T_BIT;
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#endif /* CONFIG_COMPILER_ISA_THUMB2 */
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#endif /* CONFIG_CPU_CORTEX_M */
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thread->callee_saved.psp = (uint32_t)iframe;
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thread->arch.basepri = 0;
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#if defined(CONFIG_ARM_STORE_EXC_RETURN) || defined(CONFIG_USERSPACE)
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thread->arch.mode = 0;
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#if defined(CONFIG_ARM_STORE_EXC_RETURN)
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thread->arch.mode_exc_return = DEFAULT_EXC_RETURN;
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#endif
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#if FP_GUARD_EXTRA_SIZE > 0
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if ((thread->base.user_options & K_FP_REGS) != 0) {
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thread->arch.mode |= Z_ARM_MODE_MPU_GUARD_FLOAT_Msk;
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}
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#endif
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#if defined(CONFIG_USERSPACE)
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thread->arch.priv_stack_start = 0;
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#endif
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#endif
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/*
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* initial values in all other registers/thread entries are
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* irrelevant.
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*/
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}
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#if defined(CONFIG_MPU_STACK_GUARD) && defined(CONFIG_FPU) \
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&& defined(CONFIG_FPU_SHARING)
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static inline void z_arm_thread_stack_info_adjust(struct k_thread *thread,
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bool use_large_guard)
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{
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if (use_large_guard) {
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/* Switch to use a large MPU guard if not already. */
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if ((thread->arch.mode &
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Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) == 0) {
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/* Default guard size is used. Update required. */
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thread->arch.mode |= Z_ARM_MODE_MPU_GUARD_FLOAT_Msk;
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#if defined(CONFIG_USERSPACE)
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if (thread->arch.priv_stack_start) {
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/* User thread */
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thread->arch.priv_stack_start +=
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FP_GUARD_EXTRA_SIZE;
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} else
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#endif /* CONFIG_USERSPACE */
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{
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/* Privileged thread */
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thread->stack_info.start +=
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FP_GUARD_EXTRA_SIZE;
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thread->stack_info.size -=
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FP_GUARD_EXTRA_SIZE;
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}
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}
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} else {
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/* Switch to use the default MPU guard size if not already. */
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if ((thread->arch.mode &
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Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) {
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/* Large guard size is used. Update required. */
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thread->arch.mode &= ~Z_ARM_MODE_MPU_GUARD_FLOAT_Msk;
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#if defined(CONFIG_USERSPACE)
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if (thread->arch.priv_stack_start) {
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/* User thread */
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thread->arch.priv_stack_start -=
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FP_GUARD_EXTRA_SIZE;
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} else
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#endif /* CONFIG_USERSPACE */
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{
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/* Privileged thread */
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thread->stack_info.start -=
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FP_GUARD_EXTRA_SIZE;
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thread->stack_info.size +=
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FP_GUARD_EXTRA_SIZE;
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}
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}
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}
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}
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/*
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* Adjust the MPU stack guard size together with the FPU
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* policy and the stack_info values for the thread that is
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* being switched in.
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*/
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uint32_t z_arm_mpu_stack_guard_and_fpu_adjust(struct k_thread *thread)
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{
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if (((thread->base.user_options & K_FP_REGS) != 0) ||
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((thread->arch.mode_exc_return & EXC_RETURN_FTYPE) == 0)) {
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/* The thread has been pre-tagged (at creation or later) with
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* K_FP_REGS, i.e. it is expected to be using the FPU registers
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* (if not already). Activate lazy stacking and program a large
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* MPU guard to safely detect privilege thread stack overflows.
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*
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* OR
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* The thread is not pre-tagged with K_FP_REGS, but it has
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* generated an FP context. Activate lazy stacking and
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* program a large MPU guard to detect privilege thread
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* stack overflows.
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*/
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FPU->FPCCR |= FPU_FPCCR_LSPEN_Msk;
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z_arm_thread_stack_info_adjust(thread, true);
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/* Tag the thread with K_FP_REGS */
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thread->base.user_options |= K_FP_REGS;
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return MPU_GUARD_ALIGN_AND_SIZE_FLOAT;
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}
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/* Thread is not pre-tagged with K_FP_REGS, and it has
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* not been using the FPU. Since there is no active FPU
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* context, de-activate lazy stacking and program the
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* default MPU guard size.
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*/
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FPU->FPCCR &= (~FPU_FPCCR_LSPEN_Msk);
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z_arm_thread_stack_info_adjust(thread, false);
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return MPU_GUARD_ALIGN_AND_SIZE;
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}
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#endif
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#ifdef CONFIG_USERSPACE
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FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
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void *p1, void *p2, void *p3)
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{
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/* Set up privileged stack before entering user mode */
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_current->arch.priv_stack_start =
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(uint32_t)z_priv_stack_find(_current->stack_obj);
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#if defined(CONFIG_MPU_STACK_GUARD)
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#if defined(CONFIG_THREAD_STACK_INFO)
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/* We're dropping to user mode which means the guard area is no
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* longer used here, it instead is moved to the privilege stack
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* to catch stack overflows there. Un-do the calculations done
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* which accounted for memory borrowed from the thread stack.
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*/
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#if FP_GUARD_EXTRA_SIZE > 0
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if ((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) {
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_current->stack_info.start -= FP_GUARD_EXTRA_SIZE;
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_current->stack_info.size += FP_GUARD_EXTRA_SIZE;
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}
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#endif /* FP_GUARD_EXTRA_SIZE */
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_current->stack_info.start -= MPU_GUARD_ALIGN_AND_SIZE;
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_current->stack_info.size += MPU_GUARD_ALIGN_AND_SIZE;
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#endif /* CONFIG_THREAD_STACK_INFO */
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/* Stack guard area reserved at the bottom of the thread's
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* privileged stack. Adjust the available (writable) stack
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* buffer area accordingly.
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*/
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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_current->arch.priv_stack_start +=
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((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) ?
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MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE;
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#else
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_current->arch.priv_stack_start += MPU_GUARD_ALIGN_AND_SIZE;
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#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
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#endif /* CONFIG_MPU_STACK_GUARD */
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z_arm_userspace_enter(user_entry, p1, p2, p3,
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(uint32_t)_current->stack_info.start,
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_current->stack_info.size -
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_current->stack_info.delta);
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CODE_UNREACHABLE;
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}
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#endif
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#if defined(CONFIG_BUILTIN_STACK_GUARD)
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/*
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* @brief Configure ARM built-in stack guard
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*
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* This function configures per thread stack guards by reprogramming
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* the built-in Process Stack Pointer Limit Register (PSPLIM).
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* The functionality is meant to be used during context switch.
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*
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* @param thread thread info data structure.
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*/
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void configure_builtin_stack_guard(struct k_thread *thread)
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{
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#if defined(CONFIG_USERSPACE)
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if ((thread->arch.mode & CONTROL_nPRIV_Msk) != 0) {
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/* Only configure stack limit for threads in privileged mode
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* (i.e supervisor threads or user threads doing system call).
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* User threads executing in user mode do not require a stack
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* limit protection.
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*/
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__set_PSPLIM(0);
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return;
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}
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/* Only configure PSPLIM to guard the privileged stack area, if
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* the thread is currently using it, otherwise guard the default
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* thread stack. Note that the conditional check relies on the
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* thread privileged stack being allocated in higher memory area
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* than the default thread stack (ensured by design).
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*/
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uint32_t guard_start =
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((thread->arch.priv_stack_start) &&
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(__get_PSP() >= thread->arch.priv_stack_start)) ?
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(uint32_t)thread->arch.priv_stack_start :
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(uint32_t)thread->stack_obj;
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__ASSERT(thread->stack_info.start == ((uint32_t)thread->stack_obj),
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"stack_info.start does not point to the start of the"
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"thread allocated area.");
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#else
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uint32_t guard_start = thread->stack_info.start;
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#endif
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#if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM)
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__set_PSPLIM(guard_start);
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#else
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#error "Built-in PSP limit checks not supported by HW"
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#endif
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}
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#endif /* CONFIG_BUILTIN_STACK_GUARD */
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#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
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#define IS_MPU_GUARD_VIOLATION(guard_start, guard_len, fault_addr, stack_ptr) \
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((fault_addr != -EINVAL) ? \
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((fault_addr >= guard_start) && \
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(fault_addr < (guard_start + guard_len)) && \
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(stack_ptr < (guard_start + guard_len))) \
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: \
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(stack_ptr < (guard_start + guard_len)))
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/**
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* @brief Assess occurrence of current thread's stack corruption
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*
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* This function performs an assessment whether a memory fault (on a
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* given memory address) is the result of stack memory corruption of
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* the current thread.
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*
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* Thread stack corruption for supervisor threads or user threads in
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* privilege mode (when User Space is supported) is reported upon an
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* attempt to access the stack guard area (if MPU Stack Guard feature
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* is supported). Additionally the current PSP (process stack pointer)
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* must be pointing inside or below the guard area.
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*
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* Thread stack corruption for user threads in user mode is reported,
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* if the current PSP is pointing below the start of the current
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* thread's stack.
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*
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* Notes:
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* - we assume a fully descending stack,
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* - we assume a stacking error has occurred,
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* - the function shall be called when handling MemManage and Bus fault,
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* and only if a Stacking error has been reported.
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*
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* If stack corruption is detected, the function returns the lowest
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* allowed address where the Stack Pointer can safely point to, to
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* prevent from errors when un-stacking the corrupted stack frame
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* upon exception return.
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*
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* @param fault_addr memory address on which memory access violation
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* has been reported. It can be invalid (-EINVAL),
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* if only Stacking error has been reported.
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* @param psp current address the PSP points to
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*
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* @return The lowest allowed stack frame pointer, if error is a
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* thread stack corruption, otherwise return 0.
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*/
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uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp)
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{
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#if defined(CONFIG_MULTITHREADING)
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const struct k_thread *thread = _current;
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if (thread == NULL) {
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return 0;
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}
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#endif
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#if (defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)) && \
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defined(CONFIG_MPU_STACK_GUARD)
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uint32_t guard_len =
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((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) ?
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MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE;
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#else
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/* If MPU_STACK_GUARD is not enabled, the guard length is
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* effectively zero. Stack overflows may be detected only
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* for user threads in nPRIV mode.
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*/
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uint32_t guard_len = MPU_GUARD_ALIGN_AND_SIZE;
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#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
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#if defined(CONFIG_USERSPACE)
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if (thread->arch.priv_stack_start) {
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/* User thread */
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if ((__get_CONTROL() & CONTROL_nPRIV_Msk) == 0U) {
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/* User thread in privilege mode */
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if (IS_MPU_GUARD_VIOLATION(
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thread->arch.priv_stack_start - guard_len,
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guard_len,
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fault_addr, psp)) {
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/* Thread's privilege stack corruption */
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return thread->arch.priv_stack_start;
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}
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} else {
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if (psp < (uint32_t)thread->stack_obj) {
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/* Thread's user stack corruption */
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return (uint32_t)thread->stack_obj;
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}
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}
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} else {
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/* Supervisor thread */
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if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start -
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guard_len,
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guard_len,
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fault_addr, psp)) {
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/* Supervisor thread stack corruption */
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return thread->stack_info.start;
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}
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}
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#else /* CONFIG_USERSPACE */
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#if defined(CONFIG_MULTITHREADING)
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if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len,
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guard_len,
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fault_addr, psp)) {
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/* Thread stack corruption */
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return thread->stack_info.start;
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}
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#else
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if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack,
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guard_len,
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fault_addr, psp)) {
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/* Thread stack corruption */
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return (uint32_t)Z_THREAD_STACK_BUFFER(z_main_stack);
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}
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#endif
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#endif /* CONFIG_USERSPACE */
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return 0;
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}
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#endif /* CONFIG_MPU_STACK_GUARD || CONFIG_USERSPACE */
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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int arch_float_disable(struct k_thread *thread)
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{
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if (thread != _current) {
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return -EINVAL;
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}
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|
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if (arch_is_in_isr()) {
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return -EINVAL;
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}
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|
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/* Disable all floating point capabilities for the thread */
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|
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/* K_FP_REG flag is used in SWAP and stack check fail. Locking
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* interrupts here prevents a possible context-switch or MPU
|
|
* fault to take an outdated thread user_options flag into
|
|
* account.
|
|
*/
|
|
int key = arch_irq_lock();
|
|
|
|
thread->base.user_options &= ~K_FP_REGS;
|
|
|
|
__set_CONTROL(__get_CONTROL() & (~CONTROL_FPCA_Msk));
|
|
|
|
/* No need to add an ISB barrier after setting the CONTROL
|
|
* register; arch_irq_unlock() already adds one.
|
|
*/
|
|
|
|
arch_irq_unlock(key);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int arch_float_enable(struct k_thread *thread, unsigned int options)
|
|
{
|
|
/* This is not supported in Cortex-M and Cortex-R does not have FPU */
|
|
return -ENOTSUP;
|
|
}
|
|
#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
|
|
|
|
/* Internal function for Cortex-M initialization,
|
|
* applicable to either case of running Zephyr
|
|
* with or without multi-threading support.
|
|
*/
|
|
static void z_arm_prepare_switch_to_main(void)
|
|
{
|
|
#if defined(CONFIG_FPU)
|
|
/* Initialize the Floating Point Status and Control Register when in
|
|
* Unshared FP Registers mode (In Shared FP Registers mode, FPSCR is
|
|
* initialized at thread creation for threads that make use of the FP).
|
|
*/
|
|
__set_FPSCR(0);
|
|
#if defined(CONFIG_FPU_SHARING)
|
|
/* In Sharing mode clearing FPSCR may set the CONTROL.FPCA flag. */
|
|
__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));
|
|
__ISB();
|
|
#endif /* CONFIG_FPU_SHARING */
|
|
#endif /* CONFIG_FPU */
|
|
}
|
|
|
|
void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
|
|
k_thread_entry_t _main)
|
|
{
|
|
z_arm_prepare_switch_to_main();
|
|
|
|
_current = main_thread;
|
|
#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
|
|
z_thread_mark_switched_in();
|
|
#endif
|
|
|
|
/* the ready queue cache already contains the main thread */
|
|
|
|
#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
|
|
/*
|
|
* If stack protection is enabled, make sure to set it
|
|
* before jumping to thread entry function
|
|
*/
|
|
z_arm_configure_dynamic_mpu_regions(main_thread);
|
|
#endif
|
|
|
|
#if defined(CONFIG_BUILTIN_STACK_GUARD)
|
|
/* Set PSPLIM register for built-in stack guarding of main thread. */
|
|
#if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM)
|
|
__set_PSPLIM(main_thread->stack_info.start);
|
|
#else
|
|
#error "Built-in PSP limit checks not supported by HW"
|
|
#endif
|
|
#endif /* CONFIG_BUILTIN_STACK_GUARD */
|
|
|
|
/*
|
|
* Set PSP to the highest address of the main stack
|
|
* before enabling interrupts and jumping to main.
|
|
*/
|
|
__asm__ volatile (
|
|
"mov r0, %0\n\t" /* Store _main in R0 */
|
|
#if defined(CONFIG_CPU_CORTEX_M)
|
|
"msr PSP, %1\n\t" /* __set_PSP(stack_ptr) */
|
|
#endif
|
|
|
|
"movs r1, #0\n\t"
|
|
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
|
|
|| defined(CONFIG_ARMV7_R)
|
|
"cpsie i\n\t" /* __enable_irq() */
|
|
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
|
"cpsie if\n\t" /* __enable_irq(); __enable_fault_irq() */
|
|
"msr BASEPRI, r1\n\t" /* __set_BASEPRI(0) */
|
|
#else
|
|
#error Unknown ARM architecture
|
|
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
|
"isb\n\t"
|
|
"movs r2, #0\n\t"
|
|
"movs r3, #0\n\t"
|
|
"bl z_thread_entry\n\t" /* z_thread_entry(_main, 0, 0, 0); */
|
|
:
|
|
: "r" (_main), "r" (stack_ptr)
|
|
: "r0" /* not to be overwritten by msr PSP, %1 */
|
|
);
|
|
|
|
CODE_UNREACHABLE;
|
|
}
|
|
|
|
#if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_CPU_CORTEX_M)
|
|
|
|
FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(
|
|
k_thread_entry_t main_entry, void *p1, void *p2, void *p3)
|
|
{
|
|
z_arm_prepare_switch_to_main();
|
|
|
|
/* Set PSP to the highest address of the main stack. */
|
|
char *psp = Z_THREAD_STACK_BUFFER(z_main_stack) +
|
|
K_THREAD_STACK_SIZEOF(z_main_stack);
|
|
|
|
#if defined(CONFIG_BUILTIN_STACK_GUARD)
|
|
char *psplim = (Z_THREAD_STACK_BUFFER(z_main_stack));
|
|
/* Clear PSPLIM before setting it to guard the main stack area. */
|
|
__set_PSPLIM(0);
|
|
#endif
|
|
|
|
/* Store all required input in registers, to be accesible
|
|
* after stack pointer change. The function is not going
|
|
* to return, so callee-saved registers do not need to be
|
|
* stacked.
|
|
*/
|
|
register void *p1_inreg __asm__("r0") = p1;
|
|
register void *p2_inreg __asm__("r1") = p2;
|
|
register void *p3_inreg __asm__("r2") = p3;
|
|
|
|
__asm__ volatile (
|
|
#ifdef CONFIG_BUILTIN_STACK_GUARD
|
|
"msr PSPLIM, %[_psplim]\n\t"
|
|
#endif
|
|
"msr PSP, %[_psp]\n\t" /* __set_PSP(psp) */
|
|
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
|
"cpsie i\n\t" /* enable_irq() */
|
|
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
|
"cpsie if\n\t" /* __enable_irq(); __enable_fault_irq() */
|
|
"mov r3, #0\n\t"
|
|
"msr BASEPRI, r3\n\t" /* __set_BASEPRI(0) */
|
|
#endif
|
|
"isb\n\t"
|
|
"blx %[_main_entry]\n\t" /* main_entry(p1, p2, p3) */
|
|
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
|
"cpsid i\n\t" /* disable_irq() */
|
|
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
|
"msr BASEPRI, %[basepri]\n\t"/* __set_BASEPRI(_EXC_IRQ_DEFAULT_PRIO) */
|
|
"isb\n\t"
|
|
#endif
|
|
"loop: b loop\n\t" /* while (true); */
|
|
:
|
|
: "r" (p1_inreg), "r" (p2_inreg), "r" (p3_inreg),
|
|
[_psp]"r" (psp), [_main_entry]"r" (main_entry)
|
|
#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
|
, [basepri] "r" (_EXC_IRQ_DEFAULT_PRIO)
|
|
#endif
|
|
#ifdef CONFIG_BUILTIN_STACK_GUARD
|
|
, [_psplim]"r" (psplim)
|
|
#endif
|
|
:
|
|
);
|
|
|
|
CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
|
|
}
|
|
#endif /* !CONFIG_MULTITHREADING && CONFIG_CPU_CORTEX_M */
|