zephyr/arch
Diego Sueiro 816330239e arch: Add imx7d m4 soc support
The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual
Cortex A7 core and Single Cortex M4 core.

Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A7 core (running Linux) via RPmsg.

The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README

The A7 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A7 can perform these steps at bootloader level after the Linux
system has booted.

The M4 can use up to 5 different RAMs. These are the memory mapping for
A7 and M4:

+---------------+-----------------+---------------------------+
| Memory Name   | Start Address   | Size                      |
+===============+=================+===========================+
| TCML          | 0x007F8000      | 32KB                      |
+---------------+-----------------+---------------------------+
| TCMU          | 0x20000000      | 32KB                      |
+---------------+-----------------+---------------------------+
| OCRAM_S       | 0x20180000      | 32KB                      |
+---------------+-----------------+---------------------------+
| OCRAM         | 0x00900000      | 128KB                     |
+---------------+-----------------+---------------------------+
| DDR           | 0x10000000      | 256MB                     |
+---------------+-----------------+---------------------------+

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-04-11 08:27:05 +02:00
..
arc arch/quark_se_c1000_ss: Switch to SPI DW driver 2018-04-04 19:02:35 +02:00
arm arch: Add imx7d m4 soc support 2018-04-11 08:27:05 +02:00
common drivers/interrupt_controller: Introduce multi-level interrupt support 2018-02-06 22:39:05 -05:00
nios2 cleanup: replace old jira numbers with GH issues 2018-03-26 13:13:04 -04:00
posix kernel: POSIX: Compatibility layer for POSIX message queue APIs. 2018-04-03 15:30:44 -04:00
riscv32 arch: riscv32: fe310: Always-On domain adress definition 2018-04-05 08:08:08 -05:00
x86 arch/quark_se: Enable SPI port 2 as a slave only 2018-04-04 19:02:35 +02:00
xtensa xtensa, kernel/sched: Move next switch_handle selection to the scheduler 2018-03-18 16:58:12 -04:00
CMakeLists.txt Introduce cmake-based rewrite of KBuild 2017-11-08 20:00:22 -05:00
Kconfig arch: arc: Use DTS for all ARC SoCs 2018-03-23 10:13:53 +01:00