Parthiban Nallathambi b687d76d09 soc: arm: add infineon_xmc series support ... Add infineon xmc series with XMC4500 support. XMC series comes with, - CPU operates upto 120MHz - 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation) - upto 1MB flash init: clock control & gpio is not done, so SoC initialization directly relies on HAL. Core operating clock is stored in no_init section, which is kept under DSRAM1. Only DSRAM1 is used until clock support. Using PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next revision. Note: SystemInit cannot be consumed directly due to vector table + HAL linker dependency. Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>		2020-05-09 14:21:44 +02:00
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arc	dts: Rename DT_HAS_NODE macro to DT_HAS_NODE_STATUS_OKAY	2020-05-06 05:25:41 -05:00
arm	soc: arm: add infineon_xmc series support	2020-05-09 14:21:44 +02:00
nios2	soc: nios2: Cleanup linker scripts to use new DTS macros	2020-04-30 20:59:13 -05:00
posix	kconfig: Replace defconfig singe-symbol 'if's with 'depends on'	2020-02-12 10:32:13 -06:00
riscv	dts: Rename DT_HAS_NODE macro to DT_HAS_NODE_STATUS_OKAY	2020-05-06 05:25:41 -05:00
x86	dts: Rename DT_HAS_NODE macro to DT_HAS_NODE_STATUS_OKAY	2020-05-06 05:25:41 -05:00
xtensa	soc: intel_adsp: Generalize bootloader	2020-05-09 13:07:33 +02:00
Kconfig	soc: kconfig: add SOC_DEPRECATED_RELEASE	2020-01-13 10:21:12 -05:00