7e0eed9235
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
375 lines
8.8 KiB
C
375 lines
8.8 KiB
C
/*
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* Copyright (c) 2017 Piotr Mienkowski
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* Copyright (c) 2018 Justin Watson
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam_uart
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/** @file
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* @brief UART driver for Atmel SAM MCU family.
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*
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* Note:
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* - Error handling is not implemented.
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* - The driver works only in polling mode, interrupt mode is not implemented.
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*/
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#include <errno.h>
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#include <sys/__assert.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <drivers/uart.h>
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/* Device constant configuration parameters */
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struct uart_sam_dev_cfg {
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Uart *regs;
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u32_t periph_id;
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struct soc_gpio_pin pin_rx;
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struct soc_gpio_pin pin_tx;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_config_func_t irq_config_func;
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#endif
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};
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/* Device run time data */
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struct uart_sam_dev_data {
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u32_t baud_rate;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t irq_cb; /* Interrupt Callback */
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void *irq_cb_data; /* Interrupt Callback Arg */
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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#define DEV_CFG(dev) \
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((const struct uart_sam_dev_cfg *const)(dev)->config_info)
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#define DEV_DATA(dev) \
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((struct uart_sam_dev_data *const)(dev)->driver_data)
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static int baudrate_set(Uart *const uart, u32_t baudrate,
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u32_t mck_freq_hz);
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static int uart_sam_init(struct device *dev)
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{
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int retval;
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const struct uart_sam_dev_cfg *const cfg = DEV_CFG(dev);
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struct uart_sam_dev_data *const dev_data = DEV_DATA(dev);
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Uart *const uart = cfg->regs;
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/* Enable UART clock in PMC */
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soc_pmc_peripheral_enable(cfg->periph_id);
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/* Connect pins to the peripheral */
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soc_gpio_configure(&cfg->pin_rx);
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soc_gpio_configure(&cfg->pin_tx);
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/* Reset and disable UART */
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uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX
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| UART_CR_RXDIS | UART_CR_TXDIS | UART_CR_RSTSTA;
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/* Disable Interrupts */
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uart->UART_IDR = 0xFFFFFFFF;
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/* 8 bits of data, no parity, 1 stop bit in normal mode, baud rate
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* driven by the peripheral clock, UART does not filter the receive line
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*/
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uart->UART_MR = UART_MR_PAR_NO
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| UART_MR_CHMODE_NORMAL;
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/* Set baud rate */
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retval = baudrate_set(uart, dev_data->baud_rate,
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SOC_ATMEL_SAM_MCK_FREQ_HZ);
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if (retval != 0) {
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return retval;
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}
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/* Enable receiver and transmitter */
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uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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cfg->irq_config_func(dev);
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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return 0;
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}
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static int uart_sam_poll_in(struct device *dev, unsigned char *c)
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{
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Uart *const uart = DEV_CFG(dev)->regs;
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if (!(uart->UART_SR & UART_SR_RXRDY)) {
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return -EBUSY;
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}
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/* got a character */
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*c = (unsigned char)uart->UART_RHR;
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return 0;
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}
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static void uart_sam_poll_out(struct device *dev, unsigned char c)
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{
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Uart *const uart = DEV_CFG(dev)->regs;
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/* Wait for transmitter to be ready */
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while (!(uart->UART_SR & UART_SR_TXRDY)) {
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}
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/* send a character */
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uart->UART_THR = (u32_t)c;
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}
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static int uart_sam_err_check(struct device *dev)
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{
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volatile Uart * const uart = DEV_CFG(dev)->regs;
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int errors = 0;
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if (uart->UART_SR & UART_SR_OVRE) {
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errors |= UART_ERROR_OVERRUN;
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}
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if (uart->UART_SR & UART_SR_PARE) {
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errors |= UART_ERROR_PARITY;
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}
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if (uart->UART_SR & UART_SR_FRAME) {
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errors |= UART_ERROR_FRAMING;
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}
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return errors;
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}
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static int baudrate_set(Uart *const uart, u32_t baudrate,
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u32_t mck_freq_hz)
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{
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u32_t divisor;
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__ASSERT(baudrate,
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"baud rate has to be bigger than 0");
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__ASSERT(mck_freq_hz/16U >= baudrate,
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"MCK frequency is too small to set required baud rate");
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divisor = mck_freq_hz / 16U / baudrate;
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if (divisor > 0xFFFF) {
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return -EINVAL;
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}
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uart->UART_BRGR = UART_BRGR_CD(divisor);
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return 0;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_sam_fifo_fill(struct device *dev, const uint8_t *tx_data,
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int size)
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{
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volatile Uart * const uart = DEV_CFG(dev)->regs;
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/* Wait for transmitter to be ready. */
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while ((uart->UART_SR & UART_SR_TXRDY) == 0) {
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}
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uart->UART_THR = *tx_data;
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return 1;
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}
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static int uart_sam_fifo_read(struct device *dev, uint8_t *rx_data,
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const int size)
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{
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volatile Uart * const uart = DEV_CFG(dev)->regs;
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int bytes_read;
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bytes_read = 0;
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while (bytes_read < size) {
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if (uart->UART_SR & UART_SR_RXRDY) {
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rx_data[bytes_read] = uart->UART_RHR;
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bytes_read++;
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} else {
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break;
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}
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}
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return bytes_read;
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}
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static void uart_sam_irq_tx_enable(struct device *dev)
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{
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volatile Uart * const uart = DEV_CFG(dev)->regs;
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uart->UART_IER = UART_IER_TXRDY;
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}
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static void uart_sam_irq_tx_disable(struct device *dev)
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{
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volatile Uart * const uart = DEV_CFG(dev)->regs;
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uart->UART_IDR = UART_IDR_TXRDY;
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}
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static int uart_sam_irq_tx_ready(struct device *dev)
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{
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volatile Uart * const uart = DEV_CFG(dev)->regs;
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return (uart->UART_SR & UART_SR_TXRDY);
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}
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static void uart_sam_irq_rx_enable(struct device *dev)
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{
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volatile Uart * const uart = DEV_CFG(dev)->regs;
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uart->UART_IER = UART_IER_RXRDY;
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}
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static void uart_sam_irq_rx_disable(struct device *dev)
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{
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volatile Uart * const uart = DEV_CFG(dev)->regs;
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uart->UART_IDR = UART_IDR_RXRDY;
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}
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static int uart_sam_irq_tx_complete(struct device *dev)
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{
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volatile Uart * const uart = DEV_CFG(dev)->regs;
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return !(uart->UART_SR & UART_SR_TXRDY);
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}
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static int uart_sam_irq_rx_ready(struct device *dev)
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{
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volatile Uart * const uart = DEV_CFG(dev)->regs;
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return (uart->UART_SR & UART_SR_RXRDY);
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}
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static void uart_sam_irq_err_enable(struct device *dev)
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{
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volatile Uart * const uart = DEV_CFG(dev)->regs;
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uart->UART_IER = UART_IER_OVRE | UART_IER_FRAME | UART_IER_PARE;
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}
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static void uart_sam_irq_err_disable(struct device *dev)
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{
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volatile Uart * const uart = DEV_CFG(dev)->regs;
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uart->UART_IDR = UART_IDR_OVRE | UART_IDR_FRAME | UART_IDR_PARE;
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}
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static int uart_sam_irq_is_pending(struct device *dev)
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{
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volatile Uart * const uart = DEV_CFG(dev)->regs;
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return (uart->UART_IMR & (UART_IMR_TXRDY | UART_IMR_RXRDY)) &
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(uart->UART_SR & (UART_SR_TXRDY | UART_SR_RXRDY));
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}
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static int uart_sam_irq_update(struct device *dev)
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{
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ARG_UNUSED(dev);
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return 1;
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}
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static void uart_sam_irq_callback_set(struct device *dev,
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uart_irq_callback_user_data_t cb,
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void *cb_data)
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{
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struct uart_sam_dev_data *const dev_data = DEV_DATA(dev);
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dev_data->irq_cb = cb;
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dev_data->irq_cb_data = cb_data;
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}
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static void uart_sam_isr(void *arg)
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{
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struct device *dev = arg;
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struct uart_sam_dev_data *const dev_data = DEV_DATA(dev);
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if (dev_data->irq_cb) {
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dev_data->irq_cb(dev_data->irq_cb_data);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static const struct uart_driver_api uart_sam_driver_api = {
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.poll_in = uart_sam_poll_in,
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.poll_out = uart_sam_poll_out,
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.err_check = uart_sam_err_check,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_sam_fifo_fill,
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.fifo_read = uart_sam_fifo_read,
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.irq_tx_enable = uart_sam_irq_tx_enable,
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.irq_tx_disable = uart_sam_irq_tx_disable,
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.irq_tx_ready = uart_sam_irq_tx_ready,
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.irq_rx_enable = uart_sam_irq_rx_enable,
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.irq_rx_disable = uart_sam_irq_rx_disable,
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.irq_tx_complete = uart_sam_irq_tx_complete,
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.irq_rx_ready = uart_sam_irq_rx_ready,
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.irq_err_enable = uart_sam_irq_err_enable,
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.irq_err_disable = uart_sam_irq_err_disable,
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.irq_is_pending = uart_sam_irq_is_pending,
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.irq_update = uart_sam_irq_update,
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.irq_callback_set = uart_sam_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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#define UART_SAM_DECLARE_CFG(n, IRQ_FUNC_INIT) \
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static const struct uart_sam_dev_cfg uart##n##_sam_config = { \
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.regs = (Uart *)DT_INST_REG_ADDR(n), \
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.periph_id = DT_INST_PROP(n, peripheral_id), \
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\
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.pin_rx = ATMEL_SAM_DT_PIN(n, 0), \
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.pin_tx = ATMEL_SAM_DT_PIN(n, 1), \
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\
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IRQ_FUNC_INIT \
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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#define UART_SAM_CONFIG_FUNC(n) \
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static void uart##n##_sam_irq_config_func(struct device *port) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), \
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DT_INST_IRQ(n, priority), \
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uart_sam_isr, \
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DEVICE_GET(uart##n##_sam), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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}
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#define UART_SAM_IRQ_CFG_FUNC_INIT(n) \
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.irq_config_func = uart##n##_sam_irq_config_func
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#define UART_SAM_INIT_CFG(n) \
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UART_SAM_DECLARE_CFG(n, UART_SAM_IRQ_CFG_FUNC_INIT(n))
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#else
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#define UART_SAM_CONFIG_FUNC(n)
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#define UART_SAM_IRQ_CFG_FUNC_INIT
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#define UART_SAM_INIT_CFG(n) \
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UART_SAM_DECLARE_CFG(n, UART_SAM_IRQ_CFG_FUNC_INIT)
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#endif
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#define UART_SAM_INIT(n) \
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static struct uart_sam_dev_data uart##n##_sam_data = { \
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.baud_rate = DT_INST_PROP(n, current_speed), \
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}; \
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\
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static const struct uart_sam_dev_cfg uart##n##_sam_config; \
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\
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DEVICE_AND_API_INIT(uart##n##_sam, DT_INST_LABEL(n), \
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&uart_sam_init, &uart##n##_sam_data, \
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&uart##n##_sam_config, PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&uart_sam_driver_api); \
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\
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UART_SAM_CONFIG_FUNC(n) \
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\
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UART_SAM_INIT_CFG(n);
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DT_INST_FOREACH_STATUS_OKAY(UART_SAM_INIT)
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