Mark Holden 7803a4e590 arch: riscv: ARCH_EXCEPT macro ... Enable ARCH_EXCEPT macro for non-usermode scenario for RISC-V Macro will now raise an illegal instruction exception so that mepc will hold expected value in exception handler, and generated coredump can reconstruct the failing stack Coredump tests running on renode (for RISC-V) can now utilize fatal error path through k_panic Signed-off-by: Mark Holden <mholden@fb.com>		2022-01-01 07:38:20 -05:00
..
arc	soc: arc: fix ARC_HAS_ACCL_REGS settings	2021-12-02 11:32:14 -06:00
arm	arch: cortex_m: Fix dwt cyccnt assert	2021-12-10 12:27:49 +01:00
arm64	xenvm: arm64: add Xen Enlighten and event channel support	2021-12-07 12:15:38 -05:00
common	cmake: CMake linker script generator pass handling	2021-11-08 20:45:07 +01:00
nios2	arch: nios2: Fix 10.4 violations	2021-04-10 09:59:37 -04:00
posix	pm: Remove unused parameter	2021-11-17 11:15:49 -05:00
riscv	arch: riscv: ARCH_EXCEPT macro	2022-01-01 07:38:20 -05:00
sparc	arch/sparc: Add hook for CONFIG_SCHED_THREAD_USAGE accounting in ISRs	2021-11-08 21:32:20 -05:00
x86	arch/x86: PCIE MSI vector allocator can use arch IRQ allocator	2021-12-22 12:16:52 +01:00
xtensa	soc/intel_adsp: Unify Xtensa CPU reset between cores	2021-12-14 18:43:05 -06:00
CMakeLists.txt
Kconfig	coredump: add support for RISC-V	2021-12-08 08:54:32 -05:00