The actual RISC-V core needs to select RISCV, and specific SoC CPU depend on it. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com> |
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|---|---|---|
| .. | ||
| arc | ||
| arm | ||
| arm64 | ||
| common | ||
| mips | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| CMakeLists.txt | ||
| Kconfig | ||
The actual RISC-V core needs to select RISCV, and specific SoC CPU depend on it. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com> |
||
|---|---|---|
| .. | ||
| arc | ||
| arm | ||
| arm64 | ||
| common | ||
| mips | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| CMakeLists.txt | ||
| Kconfig | ||