zephyr/soc/riscv
Ruibin Chang dc3f29f67f ITE tests/kernel/sleep: tune CONFIG_SYS_CLOCK_TICKS_PER_SEC down
We need more time to run codes because of the performance,
so I tune CONFIG_SYS_CLOCK_TICKS_PER_SEC down to reduce
the times of running k_usleep(1), then it can pass test_usleep().

Verified by follow test pattern:
west build -p always -b it8xxx2_evb tests/kernel/sleep

fixes #46208

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-07-05 11:29:43 +00:00
..
esp32c3 soc: esp32/s2/c3: pinctrl: update pin init macros 2022-07-01 16:22:18 +00:00
litex-vexriscv riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
openisa_rv32m1 riscv: Rename __irq_wrapper to _isr_wrapper 2022-06-21 20:27:20 -04:00
riscv-ite ITE tests/kernel/sleep: tune CONFIG_SYS_CLOCK_TICKS_PER_SEC down 2022-07-05 11:29:43 +00:00
riscv-privilege soc: riscv: telink_b91: add dfu related configurations for b91 platform 2022-06-24 20:25:33 +02:00
CMakeLists.txt