zephyr/dts/riscv
Olof Johansson 07ac630281 dts: riscv: add #address-cells to all interrupt controllers
This mirrors #36499 and other PRs that added them for other
architectures.

This silences a large number of dtc warnings due to the missing
property. It seems reasonable to require an address-cells property since
any interrupt controller could be the parent of an interrupt-map.

The only device actually using interrupt-maps is neorv32, and it needs
an address-cells of 2 (since this is the default if none is specified it
worked like that before this change).

While I touched this, I reordered the properties for consistency across
boards, but there's a lot of variance here already.

Signed-off-by: Olof Johansson <olof@lixom.net>
2022-07-04 14:39:43 -04:00
..
andes dts: riscv: add #address-cells to all interrupt controllers 2022-07-04 14:39:43 -04:00
espressif dts: riscv: add #address-cells to all interrupt controllers 2022-07-04 14:39:43 -04:00
gigadevice dts: riscv: add #address-cells to all interrupt controllers 2022-07-04 14:39:43 -04:00
ite dts: riscv: add #address-cells to all interrupt controllers 2022-07-04 14:39:43 -04:00
microsemi dts: riscv: add #address-cells to all interrupt controllers 2022-07-04 14:39:43 -04:00
openisa dts: riscv: add #address-cells to all interrupt controllers 2022-07-04 14:39:43 -04:00
sifive dts: riscv: add #address-cells to all interrupt controllers 2022-07-04 14:39:43 -04:00
starfive dts: riscv: add #address-cells to all interrupt controllers 2022-07-04 14:39:43 -04:00
telink dts: riscv: add #address-cells to all interrupt controllers 2022-07-04 14:39:43 -04:00
mpfs-icicle.dtsi dts: riscv: add #address-cells to all interrupt controllers 2022-07-04 14:39:43 -04:00
neorv32.dtsi dts: riscv: add #address-cells to all interrupt controllers 2022-07-04 14:39:43 -04:00
riscv32-litex-vexriscv.dtsi dts: riscv: add #address-cells to all interrupt controllers 2022-07-04 14:39:43 -04:00
virt.dtsi dts: riscv: add #address-cells to all interrupt controllers 2022-07-04 14:39:43 -04:00