This is just a stub with bits of information about RISC-V support on Zephyr, that can and should be improved over time. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com> |
||
|---|---|---|
| .. | ||
| arch | ||
| emulator | ||
| peripherals | ||
| pinctrl | ||
| porting | ||
| index.rst | ||
This is just a stub with bits of information about RISC-V support on Zephyr, that can and should be improved over time. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com> |
||
|---|---|---|
| .. | ||
| arch | ||
| emulator | ||
| peripherals | ||
| pinctrl | ||
| porting | ||
| index.rst | ||