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zephyr/tests/drivers/clock_control
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Francois Ramu a0725f039c tests: drivers: clock_control of the stm32h5 core 
Adapt the clock scheme for testing the clock on the stm32h573i_dk.
By default the HSI is 32MHz (div-by-2).
Only scheme for pll sourced by HSI is useful at max freq of 240MHz.
Configure the usart1-console clock to be csi  to always get
a valid clock source in any usecase.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-05-15 13:09:46 +02:00
..
adsp_clock samples, tests: convert string-based twister lists to YAML lists 2023-05-10 09:52:37 +02:00
clock_control_api samples, tests: convert string-based twister lists to YAML lists 2023-05-10 09:52:37 +02:00
nrf_clock_calibration samples, tests: convert string-based twister lists to YAML lists 2023-05-10 09:52:37 +02:00
nrf_lf_clock_start samples, tests: convert string-based twister lists to YAML lists 2023-05-10 09:52:37 +02:00
nrf_onoff_and_bt samples, tests: convert string-based twister lists to YAML lists 2023-05-10 09:52:37 +02:00
onoff samples, tests: convert string-based twister lists to YAML lists 2023-05-10 09:52:37 +02:00
stm32_clock_configuration tests: drivers: clock_control of the stm32h5 core 2023-05-15 13:09:46 +02:00