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zephyr/dts/xtensa/intel
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Jaroslaw Stelter 9c0dd7e3be intel_adsp: ace20_lnl: Change LNL core count to 5 
The ACE 2.0 LNL platform has 5 HIFI4 cores. Change number
of cores to enable 5th core on the platform.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-05-15 08:00:11 -04:00
..
intel_adsp_ace15_mtpm.dtsi drivers: gpdma: pm runtime works only on ace 2023-04-25 16:19:45 +02:00
intel_adsp_ace20_lnl.dtsi intel_adsp: ace20_lnl: Change LNL core count to 5 2023-05-15 08:00:11 -04:00
intel_adsp_cavs15.dtsi ace: cavs: dts: Add d-cache and i-cache line size 2022-11-23 15:39:05 -05:00
intel_adsp_cavs18.dtsi ace: cavs: dts: Add d-cache and i-cache line size 2022-11-23 15:39:05 -05:00
intel_adsp_cavs20_jsl.dtsi ace: cavs: dts: Add d-cache and i-cache line size 2022-11-23 15:39:05 -05:00
intel_adsp_cavs20.dtsi ace: cavs: dts: Add d-cache and i-cache line size 2022-11-23 15:39:05 -05:00
intel_adsp_cavs25_tgph.dtsi soc: intel_adsp: cavs: start using zephyr power management 2023-03-23 07:57:14 -04:00
intel_adsp_cavs25.dtsi soc: intel_adsp: cavs: start using zephyr power management 2023-03-23 07:57:14 -04:00
intel_adsp_cavs.dtsi dma: dts: gpdma: Add controller attributes to DT 2022-11-23 15:36:31 -05:00