zephyr/dts/riscv
Tyler Ng 1c4889e402 dts: riscv: lowrisc: Add pwrmgr node to OpenTitan Earlgrey devicetree
Adds the pwrmgr devicetree node. This is a simple binding that holds
only the address of the registers for now.

This patch is part of the OpenTitan watchdog (AON Timer) support patch
series. It is needed to ensure that the watchdog reset functionality
is enabled.

Signed-off-by: Tyler Ng <tkng@rivosinc.com>
2023-05-26 09:45:25 -04:00
..
andes dts: bindings: spi: add andes spi driver 2022-09-07 15:34:47 +02:00
espressif dts: Add missing adc dt-bindings include 2023-04-20 10:48:33 +02:00
gigadevice dts: Add missing adc dt-bindings include 2023-04-20 10:48:33 +02:00
ite ITE: drivers/usb/device: Add USB Device Controller Support 2023-05-26 12:40:18 +02:00
lowrisc dts: riscv: lowrisc: Add pwrmgr node to OpenTitan Earlgrey devicetree 2023-05-26 09:45:25 -04:00
microchip dts/riscv: move mpfs-icicle.dtsi into a common microchip directory 2023-05-04 10:47:07 +02:00
niosv dts: riscv: Add dts support for INTEL NIOSV 2023-02-20 09:29:13 -05:00
openisa
sifive dts: riscv: sifive: fu740: add more cpus 2023-04-12 13:06:29 +02:00
starfive
telink dts: riscv: telink: add DT entry for machine timer 2022-08-02 09:12:31 +02:00
neorv32.dtsi dts: riscv: neorv32: define machine timer 2022-08-02 09:12:31 +02:00
riscv32-litex-vexriscv.dtsi
virt.dtsi dts: riscv: virt: use sifive,clint0 2022-08-02 09:12:31 +02:00