Carlo Caione 034a274d93 dts: bindings: riscv: Add rv32emc variant ... To the 'riscv,isa' property enum. Signed-off-by: Carlo Caione <ccaione@baylibre.com>		2023-02-20 09:49:51 +01:00
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openisa,rv32m1-pcc.yaml	yamllint: indentation: fix dts/bindings/	2023-01-04 14:23:53 +01:00
riscv,cpus.yaml	dts: bindings: riscv: Add rv32emc variant	2023-02-20 09:49:51 +01:00
sifive-common.yaml	yamllint: indentation: fix dts/bindings/	2023-01-04 14:23:53 +01:00
sifive,e24.yaml	dts: bindings: riscv: Don't use riscv, prefix for vendor compat	2022-06-16 11:26:25 +02:00
sifive,e31.yaml	dts: bindings: riscv: Don't use riscv, prefix for vendor compat	2022-06-16 11:26:25 +02:00
sifive,e51.yaml	dts: bindings: riscv: Don't use riscv, prefix for vendor compat	2022-06-16 11:26:25 +02:00
sifive,s7.yaml	dts: bindings: riscv: Don't use riscv, prefix for vendor compat	2022-06-16 11:26:25 +02:00