2a103ea674
This test is intended to verify the interrupt nesting. Interrupt nesting feature allows an ISR to be preempted in mid-execution if a higher priority interrupt is signaled. The lower priority ISR resumes execution once the higher priority ISR has completed its processing. Signed-off-by: Ajay Kishore <ajay.kishore@intel.com>
49 lines
1011 B
C
49 lines
1011 B
C
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <ztest.h>
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#include <irq_offload.h>
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#include <kernel_structs.h>
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#define IRQ_LINE(offset) (CONFIG_NUM_IRQS - ((offset) + 1))
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#if defined(CONFIG_ARM)
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#include <arch/arm/cortex_m/cmsis.h>
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static void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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#if defined(CONFIG_SOC_TI_LM3S6965_QEMU) || defined(CONFIG_CPU_CORTEX_M0) \
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|| defined(CONFIG_CPU_CORTEX_M0PLUS)
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NVIC_SetPendingIRQ(irq);
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#else
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NVIC->STIR = irq;
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#endif
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}
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#elif defined(CONFIG_RISCV32) && !defined(CONFIG_SOC_RISCV32_PULPINO)
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static void trigger_irq(int irq)
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{
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u32_t mip;
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printk("Triggering irq : %d\n", irq);
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__asm__ volatile ("csrrs %0, mip, %1\n"
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: "=r" (mip)
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: "r" (1 << irq));
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}
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#elif defined(CONFIG_CPU_ARCV2)
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static void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_HINT, irq);
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}
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#else
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/* for not supported architecture */
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#define NO_TRIGGER_FROM_SW
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#endif
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