aec9a8c4be
Before introducing the code for ARM64 (AArch64) we need to relocate the current ARM code to a new AArch32 sub-directory. For now we can assume that no code is shared between ARM and ARM64. There are no functional changes. The code is moved to the new location and the file paths are fixed to reflect this change. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
51 lines
1.1 KiB
C
51 lines
1.1 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr.h>
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#include <kernel.h>
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#include <sys/printk.h>
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/* This function will allow execute from sram region.
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* This is needed only for this sample because by default all soc will
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* disable the execute from SRAM.
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* An application that requires that the code be executed from SRAM will
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* have to configure the region appropriately in arm_mpu_regions.c.
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*/
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#ifdef CONFIG_ARM_MPU
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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void disable_mpu_rasr_xn(void)
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{
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u32_t index;
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/* Kept the max index as 8(irrespective of soc) because the sram
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* would most likely be set at index 2.
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*/
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for (index = 0U; index < 8; index++) {
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MPU->RNR = index;
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if (MPU->RASR & MPU_RASR_XN_Msk) {
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MPU->RASR ^= MPU_RASR_XN_Msk;
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}
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}
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}
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#endif /* CONFIG_ARM_MPU */
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extern void function_in_sram2(void);
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extern void function_in_split_multiple(void);
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void main(void)
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{
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#ifdef CONFIG_ARM_MPU
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disable_mpu_rasr_xn();
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#endif /* CONFIG_ARM_MPU */
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printk("Address of main function %p\n\n", &main);
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function_in_sram2();
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function_in_split_multiple();
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}
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