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zephyr/dts/arm/st
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Aurelien Jarno 6e56cfc5cd dts: arm: st: h7: add ITCM memory for STM32H7A3 
The STM32H7A3 SoC has 64 kB of ITCM RAM mapped at address 0x00000000.

Tested using zephyr_code_relocate().

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2022-06-28 11:08:16 +02:00
..
f0 include/dt-bindings/clock: stm32: Add clock sources bindings 2022-05-10 18:42:30 +02:00
f1 dts: arm: st: f1: added DAC 2022-05-13 08:43:45 -05:00
f2 dts: migrate includes to <zephyr/...> 2022-05-06 19:54:54 +02:00
f3 include/dt-bindings/clock: stm32: Add clock sources bindings 2022-05-10 18:42:30 +02:00
f4 drivers: can: stm32: use DT_INST_FOREACH for driver setup 2022-06-22 12:25:26 +02:00
f7 dts: arm: st: f7: add ITCM memory for STM32F723 2022-06-07 18:57:33 +02:00
g0 dts: migrate includes to <zephyr/...> 2022-05-06 19:54:54 +02:00
g4 dts: arm: st: g4/u5: add missing fdcan clocks 2022-06-16 11:26:18 +02:00
h7 dts: arm: st: h7: add ITCM memory for STM32H7A3 2022-06-28 11:08:16 +02:00
l0 dts: migrate includes to <zephyr/...> 2022-05-06 19:54:54 +02:00
l1 dts: migrate includes to <zephyr/...> 2022-05-06 19:54:54 +02:00
l4 dts: fix a bunch of odd partition values dts entries 2022-05-25 14:21:04 +02:00
l5 dts: arm: stm32l5 Invalid wwdg interrupt priority 2022-05-24 08:55:16 -07:00
mp1 dts: fix a bunch of odd partition values dts entries 2022-05-25 14:21:04 +02:00
u5 dts: stm32u5: correct can1 clocks property 2022-06-22 12:29:03 +02:00
wb include/dt-bindings/clock: stm32: Add clock sources bindings 2022-05-10 18:42:30 +02:00
wl dts: migrate includes to <zephyr/...> 2022-05-06 19:54:54 +02:00