zephyr/soc
Mulin Chao b1214ead19 driver: i2c: npcx: simplify smb bank registers with union
For NPCX SMB/I2C SMB modules in FIFO mode, the registers include:

* Common registers, offset 0x00-0x0f, accessible regardless of the value
  of BNK_SEL
* Bank 0 registers, offset 0x10-0x1e, accessible if BNK_SEL is set to 0
* Bank 1 registers, offset 0x10-0x1e, accessible if BNK_SEL
is set to 1

In the current driver, it uses two structures, `smb_reg` and
`smb_fifo_reg`, to access `Common + Bank 0` and `Common + Bank 1`
registers. But It might be easy to misunderstand that they are two
different modules.

This CL tries to simplify this by the following steps:

1. Use `union` to combine `Bank 0/1` registers in the same structure.
2. Remove `smb_fifo_reg`. We needn't use two structures to present
   SMB registers.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-01-11 09:40:36 +01:00
..
arc arc: add nsim_em11d target 2022-12-19 11:56:55 +01:00
arm driver: i2c: npcx: simplify smb bank registers with union 2023-01-11 09:40:36 +01:00
arm64 board: arm64: add pinctrl support for imx93 evk board 2022-12-20 09:22:40 +01:00
mips asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
nios2 linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
posix cmake: Update CONFIG_ASAN support 2022-08-19 08:30:01 +02:00
riscv driver: systimer: increase esp32c3 tick resolution 2023-01-04 14:24:25 +01:00
sparc linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
x86 soc: x86: Used fixed BDF values for early serial 2022-11-16 11:18:43 +01:00
xtensa adsp: boot: power: Fixed used register name 2023-01-09 17:05:58 -05:00
Kconfig soc: Add ability for SOC to specify runtime CPU detection 2022-11-03 16:43:53 -04:00