dbb8ee38f2
Add driver for Microchip PolarFire SoC (MPFS) peripheral clock and soft
reset control.
Normally, the peripheral clocks and reset state are controlled by the
Hart Software Services (HSS) running on the Monitor processor. As an
alternative to using HSS services, applications can now enable the reset
controller in a device tree overly, for example:
&reset {
status = "okay";
};
&uart4 {
resets = <&reset MSS_RESET_ID_MMUART4>;
};
Embedded the reset controller node in system controller node.
Signed-off-by: Frank Kühndel <frank.kuehndel@embedded-brains.de>
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
94 lines
2.3 KiB
C
94 lines
2.3 KiB
C
/*
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* Copyright (C) 2025 embedded brains GmbH & Co. KG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_mpfs_reset
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/reset.h>
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#define SUBBLK_CLOCK_CR_OFFSET 0x84U
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#define SOFT_RESET_CR_OFFSET 0x88U
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#define RESET_MSS_REG_BIT(id) ((id) & 0x1fU)
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/* Bit 17 is related to the FPGA, bits 30 and 31 are reserved */
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#define RESET_MSS_VALID_BITS 0x3ffdffffU
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struct reset_mss_config {
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uintptr_t base;
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};
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static int reset_mss_status(const struct device *dev, uint32_t id, uint8_t *status)
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{
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const struct reset_mss_config *config = dev->config;
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/* Device is in reset if the clock is turned off or held in soft reset */
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*status = sys_test_bit(config->base + SUBBLK_CLOCK_CR_OFFSET, RESET_MSS_REG_BIT(id)) == 0 ||
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sys_test_bit(config->base + SOFT_RESET_CR_OFFSET, RESET_MSS_REG_BIT(id) != 0);
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return 0;
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}
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static int reset_mss_line_assert(const struct device *dev, uint32_t id)
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{
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const struct reset_mss_config *config = dev->config;
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unsigned int bit = RESET_MSS_REG_BIT(id);
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if (!IS_BIT_SET(RESET_MSS_VALID_BITS, bit)) {
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return -EINVAL;
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}
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/* Turn off clock */
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sys_clear_bit(config->base + SUBBLK_CLOCK_CR_OFFSET, bit);
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/* Hold in reset */
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sys_set_bit(config->base + SOFT_RESET_CR_OFFSET, bit);
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return 0;
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}
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static int reset_mss_line_deassert(const struct device *dev, uint32_t id)
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{
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const struct reset_mss_config *config = dev->config;
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unsigned int bit = RESET_MSS_REG_BIT(id);
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if (!IS_BIT_SET(RESET_MSS_VALID_BITS, bit)) {
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return -EINVAL;
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}
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/* Turn on clock */
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sys_set_bit(config->base + SUBBLK_CLOCK_CR_OFFSET, bit);
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/* Remove soft reset */
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sys_clear_bit(config->base + SOFT_RESET_CR_OFFSET, bit);
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return 0;
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}
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static int reset_mss_line_toggle(const struct device *dev, uint32_t id)
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{
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reset_mss_line_assert(dev, id);
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reset_mss_line_deassert(dev, id);
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return 0;
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}
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static DEVICE_API(reset, reset_mss_driver_api) = {
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.status = reset_mss_status,
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.line_assert = reset_mss_line_assert,
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.line_deassert = reset_mss_line_deassert,
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.line_toggle = reset_mss_line_toggle
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};
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static const struct reset_mss_config reset_mss_config = {
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.base = DT_REG_ADDR(DT_INST_PARENT(0))
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};
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DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, &reset_mss_config, PRE_KERNEL_1,
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CONFIG_RESET_INIT_PRIORITY, &reset_mss_driver_api);
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