Kai Vehmanen 7fd0a7a5eb soc: intel_adsp: replace icache ISR workaround with custom idle solution ... A workaround to avoid icache corruption was added in commit be881d4cf2 ("arch: xtensa: add isync to interrupt vector"). This patch implements a different workaround by adding custom logic to idle entry on affected Intel ADSP platforms. To safely enter "waiti" when clock gating is enabled, we need to ensure icache is both unlocked and invalidated upon entry. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>		2024-04-15 16:26:39 +02:00
..
kernel_arch_func.h	kernel: rename Z_KERNEL_STACK_BUFFER to K_KERNEL_STACK_BUFFER	2024-03-27 19:27:10 -04:00
offsets_short_arch.h	xtensa: Enable userspace	2023-11-21 15:49:48 +01:00
xtensa_asm2_context.h	arch: xtensa: Add space for HiFi registers	2024-03-05 10:57:33 +01:00
xtensa_asm2_s.h	soc: intel_adsp: replace icache ISR workaround with custom idle solution	2024-04-15 16:26:39 +02:00
xtensa_backtrace.h	xtensa: rename z_xtensa to simply xtensa	2023-12-13 09:41:24 +01:00
xtensa_internal.h	arch: move arch_interface.h under zephyr/arch	2024-03-25 09:58:35 +00:00
xtensa_mmu_priv.h	xtensa: mmu: Optimize autorefill invalidation	2024-01-19 13:50:02 +01:00
xtensa_mpu_priv.h	xtensa: mpu: enable userspace support	2024-03-19 22:17:34 -04:00