zephyr/soc/xtensa
Marc Herbert 2fac69422c boards: intel_adsp: add comments explaining log IDs start from 1
The mismatch between the slot number and the sequence ("id") made me
suspect a bug for too long. Fix one related comment and add two more. No
code change.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2021-11-07 05:34:06 -05:00
..
esp32 soc: esp32: soc does not support 2 cores 2021-10-23 20:44:26 -04:00
esp32s2 clock: esp32: unify clock control for all espressif socs 2021-11-04 15:21:26 -04:00
intel_adsp boards: intel_adsp: add comments explaining log IDs start from 1 2021-11-07 05:34:06 -05:00
intel_s1000 Revert "linker: xtensa: move IDT_LIST region" 2021-09-08 20:29:53 -05:00
nxp_adsp soc: xtensa: adsp: add support for NXP ADSP for i.MX8MP 2021-10-20 19:08:50 -04:00
sample_controller linker: align _image_text_start/end/size linker symbols name 2021-08-28 08:48:03 -04:00
CMakeLists.txt