bartoszek/zephyr
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
a57d994aaa
zephyr/drivers/interrupt_controller
History
Zide Chen 07e913a1e5 ioapic: IOREGSEL register needs to be treated as 32 bits 
If IOREGSEL register is not accessed with 32 bits, it may not be
intercepted by type 1 hypervisor correctly.

Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-07-24 09:04:05 -04:00
..
arcv2_irq_unit.c
cavs_ictl.c
cavs_ictl.h
CMakeLists.txt riscv32: riscv-privilege: integrate common code 2018-06-20 11:57:07 -04:00
dw_ictl.c drivers: interrupts: introduce Designware interrupt controller 2018-05-01 16:46:41 -04:00
dw_ictl.h drivers: interrupts: introduce Designware interrupt controller 2018-05-01 16:46:41 -04:00
exti_stm32.c driver: interrupt_controller: Add support for stm32f2 2018-07-05 11:26:07 -05:00
exti_stm32.h
i8259.c
ioapic_intr.c ioapic: IOREGSEL register needs to be treated as 32 bits 2018-07-24 09:04:05 -04:00
ioapic_priv.h
Kconfig drivers: interrupt_controller: Remove redundant 'default n' properties 2018-07-03 17:11:31 -04:00
Kconfig.multilevel drivers: interrupt_controller: Remove redundant 'default n' properties 2018-07-03 17:11:31 -04:00
Kconfig.s1000 drivers: interrupt_controller: Remove redundant 'default n' properties 2018-07-03 17:11:31 -04:00
Kconfig.shared_irq drivers: interrupt_controller: Remove redundant 'default n' properties 2018-07-03 17:11:31 -04:00
Kconfig.stm32 driver: interrupt_controller: Add support for stm32f2 2018-07-05 11:26:07 -05:00
loapic_intr.c
loapic_spurious.S
mvic.c
plic.c riscv32: riscv-privilege: Microsemi Mi-V support 2018-06-20 11:57:07 -04:00
plic.h riscv32: riscv-privilege: Microsemi Mi-V support 2018-06-20 11:57:07 -04:00
shared_irq.c
system_apic.c