f6ca7de09c
There was a lot of duplication between architectures for the definition of threads and the "nanokernel" guts. These have been consolidated. Now, a common file kernel/unified/include/kernel_structs.h holds the common definitions. Architectures provide two files to complement it: kernel_arch_data.h and kernel_arch_func.h. The first one contains at least the struct _thread_arch and struct _kernel_arch data structures, as well as the struct _callee_saved and struct _caller_saved register layouts. The second file contains anything that needs what is provided by the common stuff in kernel_structs.h. Those two files are only meant to be included in kernel_structs.h in very specific locations. The thread data structure has been separated into three major parts: common struct _thread_base and struct k_thread, and arch-specific struct _thread_arch. The first and third ones are included in the second. The struct s_NANO data structure has been split into two: common struct _kernel and arch-specific struct _kernel_arch. The latter is included in the former. Offsets files have also changed: nano_offsets.h has been renamed kernel_offsets.h and is still included by the arch-specific offsets.c. Also, since the thread and kernel data structures are now made of sub-structures, offsets have to be added to make up the full offset. Some of these additions have been consolidated in shorter symbols, available from kernel/unified/include/offsets_short.h, which includes an arch-specific offsets_arch_short.h. Most of the code include offsets_short.h now instead of offsets.h. Change-Id: I084645cb7e6db8db69aeaaf162963fe157045d5a Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
132 lines
3.0 KiB
C
132 lines
3.0 KiB
C
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Full C support initialization
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*
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*
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* Initialization of full C support: zero the .bss, copy the .data if XIP,
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* call _Cstart().
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*
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* Stack is available in this module, but not the global data/bss until their
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* initialization is performed.
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*/
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#include <stdint.h>
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#include <toolchain.h>
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#include <linker-defs.h>
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#include <arch/arc/v2/aux_regs.h>
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#include <kernel_structs.h>
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#include <nano_internal.h>
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/**
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*
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* @brief Disable the i-cache if present
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*
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* For those ARC CPUs that have a i-cache present,
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* invalidate the i-cache and then disable it.
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*
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* @return N/A
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*/
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static void disable_icache(void)
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{
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unsigned int val;
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val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
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val &= 0xff; /* version field */
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if (val == 0) {
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return; /* skip if i-cache is not present */
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}
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_arc_v2_aux_reg_write(_ARC_V2_IC_IVIC, 0);
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__asm__ __volatile__ ("nop");
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_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, 1);
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}
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/**
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*
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* @brief Invalidate the data cache if present
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*
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* For those ARC CPUs that have a data cache present,
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* invalidate the data cache.
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*
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* @return N/A
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*/
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static void invalidate_dcache(void)
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{
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unsigned int val;
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val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
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val &= 0xff; /* version field */
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if (val == 0) {
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return; /* skip if d-cache is not present */
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}
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_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
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}
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/**
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*
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* @brief Adjust the vector table base
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*
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* Set the vector table base if the value found in the
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* _ARC_V2_IRQ_VECT_BASE auxiliary register is different from the
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* _VectorTable known by software. It is important to do this very early
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* so that exception vectors can be handled.
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*
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* @return N/A
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*/
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static void adjust_vector_table_base(void)
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{
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extern struct vector_table _VectorTable;
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unsigned int vbr;
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/* if the compiled-in vector table is different
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* from the base address known by the ARC CPU,
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* set the vector base to the compiled-in address.
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*/
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vbr = _arc_v2_aux_reg_read(_ARC_V2_IRQ_VECT_BASE);
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vbr &= 0xfffffc00;
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if (vbr != (unsigned int)&_VectorTable) {
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_VECT_BASE,
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(unsigned int)&_VectorTable);
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}
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}
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extern FUNC_NORETURN void _Cstart(void);
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/**
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*
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* @brief Prepare to and run C code
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*
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* This routine prepares for the execution of and runs C code.
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*
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* @return N/A
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*/
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void _PrepC(void)
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{
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disable_icache();
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invalidate_dcache();
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adjust_vector_table_base();
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_bss_zero();
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_data_copy();
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_Cstart();
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CODE_UNREACHABLE;
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}
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