381cb25f63
An implementation to flush multiple d-cache lines has been added per the top-level cache.h API. ZEP-1153 was opened to express the need for MORE i-cache and d-cache APIs. For example, the current cache.h API doesn't provide a means to invalidate d-cache lines and has nothing for i-cache. I've also modified some of the i-cache related aux registers to have better names so that they won't be confused with d-cache. These changes are for ZEP-1176. Change-Id: If4c5410451cc40dcd5618fc871093c8febf7e061 Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
21 lines
645 B
Makefile
21 lines
645 B
Makefile
ccflags-y += -I$(srctree)/kernel/unified/include
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ccflags-y +=-I$(srctree)/arch/$(ARCH)/include
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obj-y += thread.o thread_entry_wrapper.o \
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cpu_idle.o fast_irq.o fatal.o fault.o \
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fault_s.o irq_manage.o cache.o \
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isr_wrapper.o regular_irq.o swap_macros.h swap.o \
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sys_fatal_error_handler.o
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obj-y += prep_c.o \
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reset.o \
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vector_table.o
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obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
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# Some ARC cores like the EM4 lack the atomic LLOCK/SCOND and
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# can't use these.
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obj-$(CONFIG_ATOMIC_OPERATIONS_CUSTOM) += atomic.o
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obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o
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obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o
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