Anas Nashif c2c6a6a245 qemu_riscv32: use hifive1 configuration ... Use hifive1 configuration for this qemu and set SYS_CLOCK_HW_CYCLES_PER_SEC to 10000000 Fixes #10043 Signed-off-by: Anas Nashif <anas.nashif@intel.com>		2018-11-05 11:00:38 -05:00
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arc	drivers: watchdog: Add dts support for QMSI based watchdog.	2018-10-14 14:16:03 -04:00
arm	drivers: watchdog: Adding watchdog support for sam SOC	2018-11-02 15:09:22 -05:00
bindings	qemu_riscv32: use hifive1 configuration	2018-11-05 11:00:38 -05:00
common	dts: arm: ti: Remove use of CONFIG_SOC_* from TI SoC dts files	2018-09-14 10:43:47 -05:00
nios2	dts: Add missing 'compatible' property in flash base nodes	2018-09-21 07:23:49 -07:00
riscv32	qemu_riscv32: use hifive1 configuration	2018-11-05 11:00:38 -05:00
x86	dts: x86: Fix dts warnings when building up_squared	2018-10-18 07:02:32 -05:00
xtensa	dts: intel_s1000: fix warning about leading "0x"	2018-10-19 17:52:45 -04:00
Kconfig	dts: Add support for Nordic QDEC	2018-10-17 13:45:51 -05:00