a43f3bade8
Fix the header guards, comments, github labeler, CODEOWNERS and MAINTAINERS files. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
91 lines
1.8 KiB
C
91 lines
1.8 KiB
C
/*
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* Copyright (c) 2015, Wind River Systems, Inc.
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* Copyright (c) 2017, Oticon A/S
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* "Arch" bit manipulation functions in non-arch-specific C code (uses some
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* gcc builtins)
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_SYS_IO_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM64_SYS_IO_H_
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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#include <sys/sys_io.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Memory mapped registers I/O functions */
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/*
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* We need to use explicit assembler instruction there, because with classic
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* "volatile pointer" approach compiler might generate instruction with
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* immediate value like
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*
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* str w4, [x1], #4
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*
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* Such instructions produce invalid syndrome in HSR register, so hypervisor
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* can't emulate MMIO when it traps memory access.
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*/
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static ALWAYS_INLINE uint8_t sys_read8(mem_addr_t addr)
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{
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uint8_t val;
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__asm__ volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr));
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__DMB();
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return val;
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}
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static ALWAYS_INLINE void sys_write8(uint8_t data, mem_addr_t addr)
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{
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__DMB();
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__asm__ volatile("strb %w0, [%1]" : : "r" (data), "r" (addr));
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}
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static ALWAYS_INLINE uint16_t sys_read16(mem_addr_t addr)
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{
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uint16_t val;
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__asm__ volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr));
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__DMB();
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return val;
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}
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static ALWAYS_INLINE void sys_write16(uint16_t data, mem_addr_t addr)
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{
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__DMB();
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__asm__ volatile("strh %w0, [%1]" : : "r" (data), "r" (addr));
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}
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static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr)
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{
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uint32_t val;
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__asm__ volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
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__DMB();
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return val;
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}
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static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr)
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{
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__DMB();
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__asm__ volatile("str %w0, [%1]" : : "r" (data), "r" (addr));
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM64_SYS_IO_H_ */
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