zephyr/soc
Andy Ross a42da8dcdb soc/intel_adsp: Minimize bootloader linker script
The memory layout for the boot loader was needlessly complicated, with
separate fixed regions defined at fixed addresses, all in a file that
needs to be contiguous and DMA'd from the host in a single block.  The
end result was a lot of magic numbers and wasted space.

Clean things up so that it links in a single region expressed (for the
benefit of rimage, I think) as a single program header in the ELF
file.

This is in preparation for further changes to unify the bootloader
stage with the main Zephyr image in a single link.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-07 12:07:53 -05:00
..
arc soc: arc: fix ARC_HAS_ACCL_REGS settings 2021-12-02 11:32:14 -06:00
arm drivers: counter: NXP SNVS rtc: Add support for NXP imx SNVS RTC 2021-12-07 09:45:43 -06:00
arm64 xenvm: switch to Xen PV console instead of PL011 SBSA 2021-10-29 15:23:33 +02:00
nios2
posix posix: Add missing include 2021-04-27 13:17:36 -04:00
riscv soc: it8xxx2: cleanup: Obsolete PS/2 registers definitions removal 2021-12-01 13:50:27 -06:00
sparc boards: set CPU_HAS_FPU on LEON3 soc and boards 2020-12-04 14:33:43 +02:00
x86 bluetooth: remove Kconfig options CONFIG_BT_*_ON_DEV_NAME 2021-08-25 18:05:17 -04:00
xtensa soc/intel_adsp: Minimize bootloader linker script 2021-12-07 12:07:53 -05:00
Kconfig kconfig: soc and shield cleanup 2021-06-11 16:13:22 +02:00