1e1830de95
This board, whose hardware is just a cAVS 1.8 device without an x86 host CPU, started life (as all the cAVS devices did) as a cut-and-pasted copy of the same basic code. Because of hardware and schedule limitations, it didn't get the same unification treatment that all the other platforms did. But it turns out that in SMP configurations (which... it's not clear if we actually test on hardware?) it wants to use the cavs_timer driver, which now uses the new SOC API and not the old one. Which s1000 doesn't expose. So... I guess we have to continue to cut and paste until we can find time to unify this. Add a copy of the new shim/IDC headers to this SOC and expose them via devivcetree. Signed-off-by: Andy Ross <andrew.j.ross@intel.com> |
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| .. | ||
| arc | ||
| arm | ||
| arm64 | ||
| bindings | ||
| common | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| binding-template.yaml | ||
| Kconfig | ||