Nicolas Pitre 373f8acaa7 tests: riscv: test FPU sharing access behavior ... The RISC-V FPU context switching code is intricate and sometimes subtle. Here's a test that exercizes various code paths to ensure they work as intended, and to confirm that the target hardware does behave as expected too. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>		2023-01-30 23:47:36 +00:00
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arc/arc_dsp_sharing	DSP: add dsp unit test	2022-12-19 11:56:55 +01:00
arm	Revert "tests: update expected exception codes"	2023-01-27 18:09:32 +09:00
arm64	tests: arm_smc_call: introduce arm smc call test	2022-09-09 16:36:37 +00:00
common	tests: arch: common: timing: Convert CONFIG_MP_NUM_CPUS handling	2022-10-27 14:43:55 -04:00
riscv/fpu_sharing	tests: riscv: test FPU sharing access behavior	2023-01-30 23:47:36 +00:00
x86	tests/x86/pagetables: Check pinned memory flags	2023-01-30 23:46:55 +00:00