zephyr/soc
Andy Ross a0a9a67e58 soc/intel_adsp: Fix timing/clock register ownership on cAVS 1.8+
The wall clock timer is not (per documentation) part of the
"timestamping" register set on the DSP.  And its counter and
comparator registers work fine always.  But if the DSP isn't set as
the "owner" of the timestamp hardware, wall clock interrupts never
arrive.

Also grab the PLL ownership too, because SOF already does anyway.
While we don't have a dynamic clock driver yet, we will surely want
one soon and will needt this.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-09-03 07:19:34 -04:00
..
arc boards: arc: add a nsim_hs_mpuv6 board simulator 2021-08-27 11:45:43 -04:00
arm modules: nxp_imx: Add HAS_MCUX_FLEXSPI to mimxrt1024 2021-09-02 22:40:15 -04:00
arm64 linker: align _image_text_start/end/size linker symbols name 2021-08-28 08:48:03 -04:00
nios2 soc: nios2: Cleanup linker scripts to use new DTS macros 2020-04-30 20:59:13 -05:00
posix posix: Add missing include 2021-04-27 13:17:36 -04:00
riscv soc: andes_v5: linker: fix many linker symbols name 2021-09-01 12:27:14 -04:00
sparc boards: set CPU_HAS_FPU on LEON3 soc and boards 2020-12-04 14:33:43 +02:00
x86 bluetooth: remove Kconfig options CONFIG_BT_*_ON_DEV_NAME 2021-08-25 18:05:17 -04:00
xtensa soc/intel_adsp: Fix timing/clock register ownership on cAVS 1.8+ 2021-09-03 07:19:34 -04:00
Kconfig kconfig: soc and shield cleanup 2021-06-11 16:13:22 +02:00