Jose Alberto Meza 5d34891ae0 soc: arm: microchip: mec172x: Correct PECI base address ... Use correct device tree entry Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>		2022-12-07 09:45:25 -06:00
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arc	ARC: control shared (common) interrupts via IDU	2022-11-28 17:44:54 +01:00
arm	soc: arm: microchip: mec172x: Correct PECI base address	2022-12-07 09:45:25 -06:00
arm64	boards/arm64: Add QEMU Virt KVM support	2022-11-17 11:16:08 +01:00
mips	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
nios2	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
posix	cmake: Update CONFIG_ASAN support	2022-08-19 08:30:01 +02:00
riscv	pm: esp32c3: system power management	2022-12-05 15:09:53 +01:00
sparc	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
x86	soc: x86: Used fixed BDF values for early serial	2022-11-16 11:18:43 +01:00
xtensa	pm: esp32s2: system power management	2022-12-05 15:09:53 +01:00
Kconfig	soc: Add ability for SOC to specify runtime CPU detection	2022-11-03 16:43:53 -04:00