9cb8dcbf84
The 16 bit bootstrap code for SMP CPUs was using the 286-era "lmsw" instruction (load machine status word) to set the protected bit in CR0 (which is the modern evolution of the same register), presumably because this is 16 bit code and we can't move a dword into CR0. But that's wrong, because the full instruction set *is* available in real mode on a 386, you just have to use a operand size prefix to get to it, which the assembler emits for you automatically when you use the .code16 directive. Write this conventionally and use modern (e.g. 1986-era) instructions. It also has the advantage of not confusing much more modern hypervisors like ACRN by issuing instructions they (and I!) never knew existed. Fixes #35076 Signed-off-by: Andy Ross <andrew.j.ross@intel.com> |
||
|---|---|---|
| .. | ||
| arc | ||
| arm | ||
| arm64 | ||
| common | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| CMakeLists.txt | ||
| Kconfig | ||