Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and .yaml files. Will avoid failures with the new CI test in https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only checks changed files. Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst to get rid of the trailing blank line there. It was probably misplaced. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
43 lines
440 B
Plaintext
43 lines
440 B
Plaintext
# DecaWave DWM1001 board configuration
|
|
|
|
# Copyright (c) 2019 Stéphane D'Alu
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
if BOARD_DECAWAVE_DWM1001_DEV
|
|
|
|
config BOARD
|
|
default "decawave_dwm1001_dev"
|
|
|
|
if ADC
|
|
|
|
config ADC_0
|
|
default y
|
|
|
|
endif # ADC
|
|
|
|
if I2C
|
|
|
|
config I2C_0
|
|
default y
|
|
|
|
endif # I2C
|
|
|
|
if PWM
|
|
|
|
config PWM_0
|
|
default y
|
|
|
|
endif # PWM
|
|
|
|
if SPI
|
|
|
|
config SPI_1
|
|
default y
|
|
|
|
endif # SPI
|
|
|
|
config BT_CTLR
|
|
default BT
|
|
|
|
endif # BOARD_DECAWAVE_DWM1001_DEV
|