3aa59a6eed
The gen_isr_table test now tries to install two dynamic IRQ handlers. RISCV32 has a workaround due to limited number of SW triggerable interrupts that can be configured. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
3 lines
42 B
Plaintext
3 lines
42 B
Plaintext
CONFIG_TEST=y
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CONFIG_DYNAMIC_INTERRUPTS=y
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