zephyr/arch/xtensa/core
Daniel Leung 5539c3ed90 xtensa: add calling entry point for multi-processing
Under multi-processing, only the first CPU#0 needs to go through
setting up the kernel structs and clearing out BSS (among others).
There is no need for other CPUs to do those tasks. Since each
Xtensa core starts using the same boot vector, CPUs other than #0
need to skip all the startup tasks by not calling to z_cstart().
So provide another entry point for those CPUs. Note that Xtensa
arch is highly configurable. So the implementation of the entry
point is up to each individual SoC config.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-03-25 19:07:28 -04:00
..
offsets headers: Refactor kernel and arch headers. 2019-11-06 16:07:32 -08:00
startup Revert "arch: xtensa: Use reset-vector.S in booloader code" 2020-02-08 10:01:24 +02:00
atomic.S kernel: add APIs for atomic os on pointers 2020-03-10 10:18:16 -04:00
CMakeLists.txt arch: xtensa: Add support for Intel Apollolake 2020-02-05 10:43:25 -05:00
cpu_idle.c tracing: move headers under include/tracing 2020-02-07 15:58:05 -05:00
crt1.S xtensa: add calling entry point for multi-processing 2020-03-25 19:07:28 -04:00
fatal.c xtensa: add support to build HAL as part of build process 2019-12-18 20:24:18 -05:00
irq_manage.c arch: xtensa: Add support for Intel Apollolake 2020-02-05 10:43:25 -05:00
irq_offload.c kernel: rename z_arch_ to arch_ 2019-11-07 15:21:46 -08:00
window_vectors.S headers: Refactor kernel and arch headers. 2019-11-06 16:07:32 -08:00
xtensa_intgen.py xtensa: xtensa_intgen.py: Change 'not lvl in ...' to 'lvl not in ...' 2019-09-07 07:55:01 -04:00
xtensa_intgen.tmpl
xtensa-asm2-util.S xtensa: save/restore scompare1 during context switch 2020-02-27 12:42:26 +02:00
xtensa-asm2.c kernel: rename z_arch_ to arch_ 2019-11-07 15:21:46 -08:00