5bbc6eef9f
Enable support for using an external clock as the main clock. When bypass mode is enabled, the external crystal oscillator is bypassed, and the main clock is directly driven by an external clock signal. Signed-off-by: Perry Hung <perry@mosi.io>
109 lines
3.4 KiB
Plaintext
109 lines
3.4 KiB
Plaintext
# Atmel SAM MCU series general configuration options
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# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L
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menu "Clocks"
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config SOC_ATMEL_SAM_EXT_SLCK
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bool "Use external crystal oscillator for slow clock"
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help
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Says y if you want to use external 32 kHz crystal oscillator to drive
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the slow clock. Note that this adds a few seconds to boot time, as the
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crystal needs to stabilize after power-up.
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Says n if you do not need accurate and precise timers. The slow clock
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will be driven by the internal fast RC oscillator running at 32 kHz.
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config SOC_ATMEL_SAM_EXT_MAINCK
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bool "Use external crystal oscillator for main clock"
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default y
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help
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The main clock is being used to drive the PLL, and thus driving the
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processor clock.
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Says y if you want to use external crystal oscillator to drive the
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main clock. Note that this adds about a second to boot time, as the
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crystal needs to stabilize after power-up.
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The crystal used here can be from 3 to 20 MHz.
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Says n here will use the internal fast RC oscillator running at 12 MHz.
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config SOC_ATMEL_SAM_EXT_MAINCK_BYPASS
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bool "Use bypass mode for external crystal oscillator"
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depends on SOC_ATMEL_SAM_EXT_MAINCK
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help
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When bypass mode is enabled, the external crystal oscillator is bypassed,
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and the main clock is directly driven by an external clock signal.
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Says y here if you want to use an external clock signal directly instead
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of the crystal oscillator.
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Says n here to use the external crystal oscillator normally.
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menu "PLL A"
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config SOC_ATMEL_SAM_PLLA_MULA
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int "PLL MULA"
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default 6 if SOC_SERIES_SAM3X
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default 9 if SOC_SERIES_SAM4S || SOC_SERIES_SAM4E
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default 24 if SOC_SERIES_SAMX7X
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range 1 62
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help
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This is the multiplier (MULA) used by the PLL.
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The processor clock is (MAINCK * (MULA + 1) / DIVA).
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Board config file can override this settings for a particular board.
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With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times
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the main clock frequency.
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config SOC_ATMEL_SAM_PLLA_DIVA
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int "PLL DIVA"
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default 1
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range 1 $(UINT8_MAX)
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help
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This is the divider (DIVA) used by the PLL.
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The processor clock is (MAINCK * (MULA + 1) / DIVA).
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Board config file can override this settings
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for a particular board.
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With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times
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the main clock frequency.
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config SOC_ATMEL_SAM_MDIV
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int "MDIV"
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depends on SOC_SERIES_SAMX7X
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default 2
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range 1 4
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help
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This divisor defines a ratio between processor clock (HCLK)
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and master clock (MCK) where the maximum value is 150MHz:
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MCK = HCLK / MDIV
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endmenu # PLL A
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endmenu # clocks
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config SOC_ATMEL_SAM_WAIT_MODE
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bool "CPU goes to Wait mode instead of Sleep mode"
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depends on SOC_ATMEL_SAM_EXT_MAINCK
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default y if DEBUG
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help
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For JTAG debugging CPU clock (HCLK) should not stop. In order to
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achieve this, make CPU go to Wait mode instead of Sleep mode while
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using external crystal oscillator for main clock.
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config SOC_ATMEL_SAM_DISABLE_ERASE_PIN
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bool "Disable ERASE pin"
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help
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At reset ERASE pin is configured in System IO mode. Asserting the
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ERASE pin at '1' will completely erase Flash memory. Setting this
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option will switch the pin to general IO mode giving control of the
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pin to the GPIO module.
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endif # SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L
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