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zephyr/dts/bindings/interrupt-controller
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Martí Bolívar f5a91d7a3f dts: use 'cdns' instead of 'xtensa' vendor prefix 
These IP blocks' vendor is Cadence, whose proper vendor prefix is
'cdns' if we are going to match the Linux vendor prefixes list.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-08-17 17:51:57 -04:00
..
arm,gic.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
arm,v6m-nvic.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
arm,v7m-nvic.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
arm,v8.1m-nvic.yaml arch: arm: Add initial support for Cortex-M55 Core 2021-03-23 13:13:32 -05:00
arm,v8m-nvic.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
atmel,sam0-eic.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
cdns,xtensa-core-intc.yaml dts: use 'cdns' instead of 'xtensa' vendor prefix 2021-08-17 17:51:57 -04:00
cypress,psoc6-int-mux.yaml soc: arm: cypress: psoc6: Add Cortex-M0+ int mux support 2021-01-20 17:54:09 -06:00
cypress,psoc6-intmux-ch.yaml soc: arm: cypress: psoc6: Add Cortex-M0+ int mux support 2021-01-20 17:54:09 -06:00
espressif,esp32-intc.yaml esp32: drivers: interrupt_controller: add interrupt allocation support 2021-07-16 07:19:28 -04:00
gaisler,irqmp.yaml dts: bindings: remove default usage in gaisler,irqmp 2021-02-03 13:41:47 -05:00
intel,cavs-intc.yaml intc: intc_cavs: Use DTS labels for device names 2020-04-22 04:59:22 -05:00
intel,ioapic.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
intel,vt-d.yaml dts: Add bindings for Intel VT-D interrupt remapper device 2020-12-08 09:29:20 -05:00
interrupt-controller.yaml dts: bindings: Shorten license headers 2019-09-07 10:25:02 -05:00
ite,it8xxx2-intc.yaml dts: it8xxx2 device tree and binding 2020-12-16 08:47:36 -05:00
microchip,xec-ecia-girq.yaml Microchip: MEC172x Add aggregated interrupt driver 2021-07-26 12:24:52 -04:00
microchip,xec-ecia.yaml Microchip: MEC172x Add aggregated interrupt driver 2021-07-26 12:24:52 -04:00
nuvoton,npcx-miwu-int-map.yaml dts: npcx: Fixed the name of nodes in vw, miwu-wui, and miwu-int files. 2021-04-13 13:00:19 -04:00
nuvoton,npcx-miwu-wui-map.yaml driver: intc: add MIWU driver support in NPCX series. 2020-09-01 13:35:25 +02:00
nuvoton,npcx-miwu.yaml driver: intc: add MIWU driver support in NPCX series. 2020-09-01 13:35:25 +02:00
openisa,rv32m1-event-unit.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
openisa,rv32m1-intmux-ch.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
openisa,rv32m1-intmux.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
riscv,clint0.yaml dts/bindings: Add binding for riscv,clint0 2020-11-19 17:00:46 -05:00
riscv,cpu-intc.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
riscv,plic0.yaml dts: bindings: add IRQ priority support for SiFive PLIC 2021-01-14 12:43:58 -06:00
shared-irq.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
sifive,plic-1.0.0.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
snps,archs-idu-intc.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
snps,arcv2-intc.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
snps,designware-intc.yaml drivers/interrupt-controller: Make irqs DT configured in DW 2020-01-28 18:18:18 -05:00
st,stm32-exti.yaml dts: stm32: Add exti nodes to stm32 series 2021-02-17 14:26:23 -06:00
swerv,pic.yaml dts: bindings: Remove 'title:' and put all info. into 'description:' 2019-12-18 11:52:45 +01:00
vexriscv-intc0.yaml dts: rename 'vexriscv,intc0' compatible to 'vexriscv-intc0' 2021-08-17 17:51:57 -04:00