37bbe7aeea
A simple WAITI isn't sufficient in all cases. The cAVS 2.5 hardware uses WAITI as the entry state for per-core power gating, which is very difficult to debug. Provide a fallback that simply spins in the idle loop waiting for interrupts to provide a stable system while this feature stabilizes. Also, the SOF code for those platforms references a known bug with the Xtensa LX6 core IP (or at least some versions), and will prefix the WAIT instruction with 128 NOP.N's followed by an ISYNC and EXTW. This bug hasn't been seen under Zephyr yet, and details are sketchy. But the code is simply enough to import and works correctly. Place both workaround under new kconfig variables and select them both (even though they're actually mutually exclusive -- if you select both CPU_IDLE_SPIN overrides) for cavs_v25. Signed-off-by: Andy Ross <andrew.j.ross@intel.com> |
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| core | ||
| include | ||
| CMakeLists.txt | ||
| Kconfig | ||