8ac6f74a7d
Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds support for the "sample_controller" SoC (used by qemu_xtensa) as demonstration. As Xtensa lacks a common linker script at the arch level, enabling it for each platform will be a piecemeal effort. This patch adds it to the `soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is set to be called "RAM", and hooks are inserted so that gen_relocate_app.py can add the relevant linker bits. Also, `tests/application_developent/code_relocation` was tweaked to support the qemu_xtensa platform. Basically, add the relevant linker script and ensure that relevant memory regions have their program header (PHDR) associated. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
26 lines
1.1 KiB
YAML
26 lines
1.1 KiB
YAML
common:
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tags: linker
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tests:
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tests.application_development.code_relocation:
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filter: not CONFIG_CPU_HAS_NXP_MPU and CONFIG_MINIMAL_LIBC and dt_chosen_enabled("zephyr,itcm")
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arch_allow: arm
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extra_configs:
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- CONFIG_RELOCATE_TO_ITCM=y
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tests.application_development.code_relocation_kinetis:
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filter: CONFIG_CPU_HAS_NXP_MPU and CONFIG_MINIMAL_LIBC and dt_chosen_enabled("zephyr,itcm")
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arch_allow: arm
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extra_configs:
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- CONFIG_RELOCATE_TO_ITCM=y
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- CONFIG_MPU_ALLOW_FLASH_WRITE=y
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tests.application_development.code_relocation.no_itcm:
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filter: not CONFIG_CPU_HAS_NXP_MPU and not dt_chosen_enabled("zephyr,itcm")
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arch_allow: arm
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extra_sections: _SRAM2_RODATA_SECTION_NAME _SRAM_TEXT_SECTION_NAME _SRAM_RODATA_SECTION_NAME _SRAM_DATA_SECTION_NAME _CUSTOM_SECTION_NAME2
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platform_allow: qemu_cortex_m3 mps2_an385 sam_e70_xplained
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tests.application_development.code_relocation.riscv:
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extra_args: CONF_FILE="prj_riscv.conf"
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platform_allow: qemu_riscv32 qemu_riscv64
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tests.application_development.code_relocation.xtensa:
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extra_args: CONF_FILE="prj_xtensa.conf"
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platform_allow: qemu_xtensa
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